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this is information on a product in full production. september 2015 docid027110 rev 2 1/114 VX6854LC qxga edof camera module datasheet - production data features ? 3.15 megapixel resolution sensor (2048 x1536) ? extended depth of field (edof) ? compact size: 6.5 x 6.5 x 4.6mm ? smia profile 2 compliant ? mipi (a) csi-2 (v0.9 d-phy) and smia ccp2 video data interface ? cci command interface 100 khz up to 400 khz ? 2.8v (analog) / 1.8v (digital) operation ? integral emc shielding ? binning mode (2x2) ? defect correction ? 4-channel lens shading correction description the VX6854LC 3 megapixel camera module is designed to be used for high quality still camera function and also supports video modes. the camera silicon device is smia 1.0 profile 2 compliant and is capable of generating raw bayer 3 mpixel images up to 20 fps. the VX6854LC supports the cci control and ccp 2.0 and csi-2 data interfaces. the module design is optimized for both footprint and height. the module provides excellent image quality at focus distances from less than 50 cm to infinity. VX6854LC offers an ultra low power consumption hardware standby mode consuming less than 50 w (typical). a separate hardware accelerator (stv0987) device can be incorporated in the phone system to run the associated image processing algorithms in hardware where the baseband cannot support this processing load. a. copyright ? mipi alliance standard for camera serial interface 2v1.0 and mipi al liance specification d-phy v 0.9 table 1. device summary order code package packing VX6854LCq05i/1 smia65 tape and reel www.st.com
contents VX6854LC 2/114 docid027110 rev 2 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 VX6854LC use in system with hardware co-processor . . . . . . . . . . . . . . 13 1.2 VX6854LC use in system with software image processing . . . . . . . . . . . 14 1.3 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 esd protection diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 analog video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 digital video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.1 power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.3 internal power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.4 failsafe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 clock and frame rate timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.1 video frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.2 pll and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.3 clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 control and video interface formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.1 ccp/csi-2 serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6.2 cci serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 status registers [0x0000 to 0x000f] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 frame format description registers [0x0040 to 0x007f] . . . . . . . . . . . . . . 31 4.3 analogue gain description registers [0x0080 to 0x0097] . . . . . . . . . . . . . 31 4.4 data format description registers [0x00c0 to 0x00ff] . . . . . . . . . . . . . . . 32 4.5 setup registers [0x0100 to 0x01ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
docid027110 rev 2 3/114 VX6854LC contents 6 4.6 integration time and gain registers [0x0200 to 0x02ff] . . . . . . . . . . . . . . 34 4.7 video timing registers [0x0300 to 0x03ff] . . . . . . . . . . . . . . . . . . . . . . . . 35 4.8 image scaling registers [0x0400 to 0x04ff] . . . . . . . . . . . . . . . . . . . . . . 36 4.9 image compression registers [0x0500 to 0x05ff] . . . . . . . . . . . . . . . . . . 37 4.10 test pattern registers [0x0600 to 0x06ff] . . . . . . . . . . . . . . . . . . . . . . . . 37 4.11 fifo water mark registers [0x0700 to 0x0701] . . . . . . . . . . . . . . . . . . . . . 38 4.12 dphy registers [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.13 binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.14 data transfer registers [0x0a00 to 0x0a02] . . . . . . . . . . . . . . . . . . . . . . . 39 4.15 shading correction registers [0x0b00 to 0x0b00] . . . . . . . . . . . . . . . . . . 39 4.16 defect correction registers [0x0b05 to 0x0b09] . . . . . . . . . . . . . . . . . . . . 40 4.17 edof registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.18 color feedback registers [0x0b8c to 0x0b95] . . . . . . . . . . . . . . . . . . . . . 41 4.19 integration time and gain parameter limit registers [0x1000 to 0x10ff] . 42 4.20 video timing parameter limit registers [0x1100 to 0x11ff] . . . . . . . . . . . . 43 4.21 image scaling parameter limit registers [0x1200 to 0x12ff] . . . . . . . . . . 47 4.22 image compression parameter registers [0x1300 to 0x13ff] . . . . . . . . . 47 4.23 color matrix registers [0x1400 to 0x14ff] . . . . . . . . . . . . . . . . . . . . . . . . 47 4.24 fifo capability registers [0x1500 to 0x15ff] . . . . . . . . . . . . . . . . . . . . . 48 4.25 csi lane mode capability registers [0x1600 to 0x1602] . . . . . . . . . . . . . . 48 4.26 binning capability registers [0x1700 to 0x1719] . . . . . . . . . . . . . . . . . . . . 49 4.27 data transfer capability registers [0x1800 to 0x1800] . . . . . . . . . . . . . . . 49 4.28 shading correction capability registers [0x1900 to 0x1900] . . . . . . . . . . . 50 4.29 defect correction capability registers [0x1903 to 0x1903] . . . . . . . . . . . . 50 4.30 edof capability registers [0x1980 to 0x19c0] . . . . . . . . . . . . . . . . . . . . . 50 4.31 color feedback capability registers [0x1987 to 0x1987] . . . . . . . . . . . . . . 51 4.32 manufacturer specific registers [0x3000 to 0x3fff] . . . . . . . . . . . . . . . . 51 5 video data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1 output size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.1 programmable addressable region of the pixel array . . . . . . . . . . . . . . 55
contents VX6854LC 4/114 docid027110 rev 2 6.1.2 programmable width and height for outpu t image data . . . . . . . . . . . . . 56 6.1.3 scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1.4 subsampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.1.5 binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.2 video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2.1 pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2.2 spread spectrum clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2.3 framerate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.2.4 derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3 bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 image compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5 exposure and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5.1 analogue gain model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5.2 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.5.3 integration and gain parameter re-timing . . . . . . . . . . . . . . . . . . . . . . . . 69 7 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.1 power supply - vdig, vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3.2 power supply (peak current) - vdig, vana . . . . . . . . . . . . . . . . . . . . . . 72 7.3.3 power supply ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4 system clock - extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.5 power down control - xshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.6 cci interface - sda, scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.6.1 cci interface - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.6.2 cci interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.7 ccp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.7.1 ccp interface - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.7.2 ccp interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.8 csi-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.8.1 csi-2 interface - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.8.2 csi-2 interface - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8 optical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
docid027110 rev 2 5/114 VX6854LC contents 6 8.1 lens characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2 text, 1d and 2d code reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.1 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.2 personality file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10 edof control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 10.1 edof capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 10.2 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 10.3 edof control registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . 87 10.3.1 edof_mode (0xb80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3.2 edof_est_focus_distance (0x0b82) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.3 edof tuning sliders (0xb83 to 0x0b85) . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.4 edof focus distance (0x0b88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.5 edof estimation control (0x0b8a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.4 super macro mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.5 edof and white balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11 image optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.1 defect correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2 mapped couplet correction (bruce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.3 lens shading correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12 nvm contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.1 sensitivity data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2 nvm map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 13 defect categorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.1 pixel defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.2 sensor array area definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13.3 pixel fault numbering convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.4 single pixel faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13.5 couplet definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 13.6 physical aberrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
contents VX6854LC 6/114 docid027110 rev 2 14 mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 15 user precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 16 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 17 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
docid027110 rev 2 7/114 VX6854LC list of tables 8 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. esd protection diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. power management matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. power-up sequence timing constraints for ccp 2/csi2 communications . . . . . . . . . . . . . . 20 table 9. power-down sequence timing constraints for csi2 communications . . . . . . . . . . . . . . . . . 23 table 10. por cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. system input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. status registers [0x0000 to 0x000f] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. frame format description registers [0x0040 to 0x00 7f] . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. analogue gain description [0x0080 to 0x0097] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. data format description registers [0x00c0 to 0x00ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. setup registers [0x0100 to 0x01ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. integration time and gain registers [0x0200 to 0x02 ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 18. video timing registers [0x0300 to 0x03ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. image scaling registers [0x0400 to 0x04ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 20. image compression registers [0x0500 to 0x05ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. test pattern registers [0x0600 to 0x06ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 22. fifo water mark registers [0x0700 to 0x0701]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. dphy registers [0x0810 to 0x0811] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 24. binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 25. data transfer registers [0x0a00 to 0x0a02] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 26. shading correction registers [0x0b00 to 0x0b00]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 27. defect correction registers [0x0b05 to 0x0b09] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 28. edof registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 table 29. color feedback registers [0x0b8c to 0x0b95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 30. integration time and gain parameter limit registers [0x1000 to 0x10ff]. . . . . . . . . . . . . . . 42 table 31. video timing parameter limit registers [0x1100 to 0x11ff]. . . . . . . . . . . . . . . . . . . . . . . . . 43 table 32. image scaling parameter limit registers [0x1200 to 0x12ff] . . . . . . . . . . . . . . . . . . . . . . . 47 table 33. image compression parameter limit registers [0x 1300 to 0x13ff] . . . . . . . . . . . . . . . . . . . 47 table 34. color matrix registers [0x1400 to 0x14ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 35. fifo capability registers [0x1500 to 0x15ff] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 36. csi llane mode capab ility registers [0x1600 to 0x16 02] . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 37. binning capability regi sters [0x1700 to 0x1719] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 38. data transfer ca pability registers [0x1800 to 0x1800]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 39. shading correction capability re gisters [0x1900 to 0x1900] . . . . . . . . . . . . . . . . . . . . . . . . 50 table 40. defect correction capability re gisters [0x1903 to 0x1903] . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 41. edof capability register s [0x1980 to 0x19c0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 42. color feedback capa bility registers [0x1987 to 0x1987] . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 43. manufacturer specific registers [0x3000 to 0x3fff]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 44. binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 45. external clock frequency examples, 3.15 mpixel raw10 20 fps (csi-2 only). . . . . . . . . . . 62 table 46. external clock frequency examples, 3.15 mpix el raw10 15 fps (csi-2 or ccp) . . . . . . . . 63 table 47. analogue gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 48. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
list of tables VX6854LC 8/114 docid027110 rev 2 table 49. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 50. power supplies vdig, vana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 51. in-rush current vdig, vana for ccp2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 52. in-rush current vdig, vana for csi-2 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 53. ripple requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 54. system clock - extclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 55. power down control - xshutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 56. cci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 57. cci interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 58. ccp interface - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 59. ccp interface - timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 60. csi-2 interface - high speed mode - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 61. csi-2 interface - low power mode - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 62. csi-2 interface - high speed mode - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 63. csi-2 interface - low power mode - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 64. lens design characteristics for first source lens supplier . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 66. edof registers [0x0b80 to 0x0b8a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 67. color feedback registers [0x0b8c - 0x0b95] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 68. nvm map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 69. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 70. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
docid027110 rev 2 9/114 VX6854LC list of figures 10 list of figures figure 1. VX6854LC camera module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. VX6854LC in system with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. VX6854LC in system wi th software image processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. VX6854LC module pinout (viewed from bottom of camera module) . . . . . . . . . . . . . . . . . 15 figure 5. overview of analog video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. system state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. VX6854LC power-up sequence for ccp2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. VX6854LC power-up sequence for csi-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. VX6854LC power-down sequence for csi-2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. por timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. clock input types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. VX6854LC ccp frame form at . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 13. VX6854LC csi-2 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 14. programmable addressable region of the pixel arra y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 15. output size within a ccp data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 16. scaling modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 17. scaler quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 18. example image full scaled by a downscale factor of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 19. sub-sample readout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 20. binning repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 21. VX6854LC clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 22. timing block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 23. smia output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 24. fifo water mark control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 25. bayer pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. analogue gain register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 27. cci ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 28. sublvds ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 29. examples of barcode and qr code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 figure 30. mobile camera applicat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 31. what is sharp? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 32. edof main principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 33. example images with different settings for sharpn ess slider . . . . . . . . . . . . . . . . . . . . . . . 88 figure 34. example images with different settings for denois ing slider . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 35. example images with different settings for nois e vs. details slider . . . . . . . . . . . . . . . . . . . 89 figure 36. focus strategy weightings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 37. processing pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 38. image showing defective pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 39. block diagram of dynamic defect correction block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 40. dynamic defect correction outp ut example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 41. corrected bayer patter n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 42. lens shading images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 43. VX6854LC pixel defect test area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 44. pixel numbering notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 45. single pixel fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 46. general couplet example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 47. test region definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 48. scan array for blemis h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
list of figures VX6854LC 10/114 docid027110 rev 2 figure 49. fail map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 50. contiguous pixel example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 51. VX6854LC outline drawing - sheet 1 of 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 52. VX6854LC outline drawing - sheet 2 of 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 53. VX6854LC outline drawing - sheet 3 of 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
docid027110 rev 2 11/114 VX6854LC overview 69 1 overview the VX6854LC image sensor produces raw 3.15 mpixel digital video data at up to 20 frames per second. the VX6854LC has both ccp2.0 and mipi csi-2 video data interfaces selectable over the camera control interface (cci). the vx6 854lc is compliant with the smia 1.0 (b) specification profile 2. the VX6854LC can also be used as profile 0 or profile 1 device. the sensor supports full horizontal and vertical sca ling and output frequency derating as defined in the specification. the VX6854LC supports 2x2 binning modes which support frame rates of 40 fps and 80 fps respectively. the image data is digitized using an internal 10 -bit column adc. the re sulting pixel data is output as 8-bit, 10-bit or 10-8 bit compressed data and includes checksums and embedded codes for synchronization. the interface conforms to both the ccp 2.0 and mipi csi-2 interface standards. the sensor is fully conf igurable through a cci serial interface. the module is available in a smop type package measuring 6.5 mm x 6.5 mm x 4.6 mm. it is designed to be used with a board mounted smia65 socket. figure 1. VX6854LC camera module b. including up to ecr0002
overview VX6854LC 12/114 docid027110 rev 2 table 2. technical specification feature detail pixel resolution 2048 x 1536 (qxga) sensor technology img140 st?s 65 nm based cmos imaging process pixel size 1.75 m x 1.75 m exposure control + 81 db analogue gain + 24 db (max) digital gain + 6 db (max) dynamic range 63 db signal to noise 36 db (@ 100 lux) snr10 value 60 lux supply voltages analogue: 2.3v - 2.9v digital: 1.7v - 1.9v average power consumption <200 mw package size (l x w x h) 6.5 mm x 6.5 mm x 4.6 mm lens 58 +/-2 hfov f/2.8 tv distortion -0.3% relative illumination 75 % (typ.) system attach smia65 socket
docid027110 rev 2 13/114 VX6854LC overview 69 1.1 VX6854LC use in system wi th hardware co-processor the VX6854LC is an image sensor and it can be paired with the stmicroelectronics stv0987 companion processor. the coprocessor and the sensor together form a complete imaging system. figure 2 below illustrates a typical system using VX6854LC and stv0987. figure 2. VX6854LC in system with processor the sensor main function is to convert the vi ewed scene into a data stream. the companion processor function is to manage the sensor so that it can produce the best possible pictures and to process the data stream into a form which is easily handled by up stream mobile baseband or mmp (multi-media processor) chipsets. the sensor supplies high speed clock signal to the processor and provides the embedded control sequences which allow the co processor to synchronize with the frame and line level timings. the processor then performs the color processing on the raw image data from the sensor before supplying the final image data to the host. with the coprocessor system the clock is se nt by host to both the VX6854LC and the coprocessor. the high-speed clock for the coprocessor is supplied from the VX6854LC. it is generated using the VX6854LC pll and is pr ovided as the continuou s data qualification clock. VX6854LC ccp 2.0 rx ccp 2.0 rx input data i/f output coder mux bayer recon- struction scaler color engine color engine house cci master cci slave keeper stv0987 mobile baseband xshut down cci xshut down cci ccp imaging cci ccp2 tx pixel array and processes extclk
overview VX6854LC 14/114 docid027110 rev 2 1.2 VX6854LC use in system with software image processing the VX6854LC image sensor can be directly connected to a baseband or multimedia processor. no dedicated coprocessor is used in this configuration. the image processing is done in software or hardware within the baseband processor. figure 3. VX6854LC in system with software image processing systems with a ccp 1.0 interface can operate with this device, however they may have a maximum ccp link speed of 208 mhz and therefore will not be able to achieve 20 fps with this device. 1.3 reference documents mobile baseband processor xshutdown extclk smia cci ccp VX6854LC imaging cci ccp2 tx pixel array and processes table 3. reference documents title date mipi alliance standard for camera se rial interface 2 (c si-2) v1.0 nov 2005 mipi alliance d-phy specific ation (v00-90-00) oct 2007 smia 1.0 functional specification 30/06/2004 smia 1.0 characterization specification rev a 10/03/2005 smia 1.0 ccp2 specification 30/06/2004 smia 1.0 mechanical specification 30/06/2004 smia 1.0 functional specification ecr0001 ver 1 11/02/2005 smia 1.0 ccp2 specification ecr0002 ver 1 11/02/2005
docid027110 rev 2 15/114 VX6854LC device pinout 69 2 device pinout figure 4 shows the module pinout and table 4 contains the signal description. figure 4. VX6854LC module pinout (viewed from bottom of camera module) table 4. pin description pad number pad name i/o type description power supplies 1 vcap pwr no connection required (1) 7 gnd pwr ground (combined) 2 vana pwr analog power 10 vdig pwr digital power system 3 xshutdown i power down control (2) 4 extclk i system clock input (3) control 5 scl i serial communication clock 6 sda i/o serial communication data data 8 clk- sublvds output output qualifying clock 9 clk+ sublvds output output qualifying clock 11 data- sublvds output serial output data 12 data+ sublvds output serial output data 1 2 3 4 5 6 7 8 9 10 11 12 t1 t2 t3 t4 t5 t6 t7 t8 xshutd datan datap vcap vana extclk scl sda vdig clkp clkn gnd
device pinout VX6854LC 16/114 docid027110 rev 2 2.1 esd protection diodes the esd protection diodes can be used to chec k the connectivity. to test for connectivity, draw 100 ua from the pin and measure the voltage. if the voltage is less than 180 mv or greater than 900 mv the test fails. st test t1-t8 st test pins do not connect (4) 1. vcap is internal to the module. an additional 220 nf capacitor may also be connected to this pin. 2. signal is active low. 3. the extclk pad has a schmitt trigger input 4. test pins are not floating. table 4. pin description (continued) pad number pad name i/o type description table 5. esd protection diodes s854 smia65 pin name pin number esd protected diode to vdig diode to gnd vcap 1 yes no yes vana 2 yes no yes xshutd 3 yes no yes extclk 4 yes no yes scl 5 yes no yes sda 6 yes no yes dgnd 7 yes yes yes clkn 8 yes diode to local supply diode to gnde clkp 9 yes diode to local supply diode to gnde vdig 10 yes no yes datan 11 yes diode to local supply yes datap 12 yes diode to local supply yes
docid027110 rev 2 17/114 VX6854LC functional description 69 3 functional description this chapter details the main blocks in the device in the following sections: ? section 3.1: analog video block ? section 3.2: digital video block ? section 3.4: power management on page 19 this chapter also describes: ? the device?s operating modes, see section 3.3 on page 18 ? clock and frame rate control, see section 3.5 on page 26 ? control and video interface formats, see section 3.6 on page 28 3.1 analog video block the analog video block, shown in figure 5 , consists of a 3.15 mpixel resolution pixel array, power management circuitry. the digital block pr ovides all timing signals to drive the analog block. figure 5. overview of analog video block pixel voltage values are read out and digitized using the address decoders and column adc. 3.15mp pixel array y address digital logic raw sensor data timing signals timing signals power management sram readout x-address column adc
functional description VX6854LC 18/114 docid027110 rev 2 3.2 digital video block 3.2.1 features ? frame rate: 20 frame/s maximum can be reduced down to less than 3 frame/s (3.15 mpixel) using frame extension ? automatic dark calibration to ensure consistent video level over varying scenes ? on-chip power-on-reset cell ? output format: 3.15 mpixel 2064 x 1552 (maximum) 3.2.2 dark calibration algorithm VX6854LC runs a dark calibration algorithm on the raw image data to control the video offsets caused by dark current. this ensures that a high quality image is output over a range of operating conditions. first frame dark level is correctly calibrated, for subsequent frames the adjustment of the dark level is damped by a leaky integrator function to avoid possible frame to frame flicker. 3.3 device operating modes figure 6 shows the various operating modes used by the system. the modes are exaplained in table 6 . figure 6. system state diagram streaming csi-2 sw-standby ccp2 sw-standby csi-2 hw-standby csi-2 power-off csi-2 streaming ccp2 cci cci cci cci cci cci power supplies on power supplies off cci and extclk stopped or xshutdown is low power supplies off cci and extclk stopped or xshutdown is low cci and extclk is running and xshutdown is high
docid027110 rev 2 19/114 VX6854LC functional description 69 3.4 power management VX6854LC requires a dual power supply. the analog circuits are powered by a nominal 2.8 v supply while the digital logic and digita l i/o are powered by a 1.8 v supply. different sections of the sensor are powered depending on the system state. see table 7 for details. table 6. operating modes mode description power off power supplies are off. hardware standby this is the lowest power consumpt ion mode. cci communications are not supported in this mode. the clock input pad, pll and the video blocks are powered down. this state is entered by pulling the control pin xshutdown down. all registers are returned to their default values. software standby this mode preserves the contents of the cci regi ster map. cci communications are supported in this mode. the software standby mode is selected using a serial interface command. if this state is entered from hardware standby the data pads remain high impedance. if this state is entered from streaming then the data pads go high impedance at the end of the current frame. at this point the video block and pll power down. the internal video timing is reset to the start of a video frame in preparation for the enabling of active video. the values of the serial interface registers like exposure and gain are pr eserved. the system clock must remain active when communicating with the sensor. this state is entered by releasing th e device from hard reset by: setting xshutdown high, writing 0x00 to the mode control register (0x0100) or commanding a soft reset by writing 0x01 to the software reset register (0x0103). note that after a soft reset or the transition of xshutdown to high, all registers are retur ned to their default values. streaming the VX6854LC streams live video. this mode is entered by writing 0x01 to the mode control register (0x0100). table 7. power management matrix mode functional block powered down video data inhibit cci digital pll and clk pins (1) 1. pll, clk+ and clk- pins output pins analog hardware standby yes yes yes yes yes yes software standby no yes yes yes yes yes streaming no no no no no no
functional description VX6854LC 20/114 docid027110 rev 2 3.4.1 power-up procedure the digital and analog supply voltages can be powered up in any order for example, vdig then vana or vana then vdig. see table 8 for timing constraints. on power-up the on-chip power-on reset cell ensures that the cci register values are initialized correctly to their default values. the extclk clock can either be initially low and then enabled during software standby mode or extclk can be a free running clock. table 8. power-up sequence timing cons traints for ccp2/csi2 communications symbol parameter min. max. units t0 vana rising ? vdig rising vana and vdig may rise in any order the rising separation can vary from 0 ns to indefinite ns t1 vdig rising ? vana rising ms t2 vana/vdig ? xshutdown rising xshutdown must rise coincident with, or later than, both power supplies (vdig and vana) us t3 xshutdown ? first i 2 c transaction with free running clock 5 (1) 1. 5 ms is necessary to upload the nvm data into fi rmware registers and get the fw ready for sensor initialization through i 2 c writes. -ms t4 minimum period with extclk present prior to the first i 2 c transaction. gated clock. 5 (2) 2. for gated clock. -ms t5 pll start up/lock time - 1 ms t6 entering streaming mode ? first frame start sequence (fixed part) -10ms t7 entering streaming mode ? first frame start sequence (variable part) = integration time fine_integration_ time_min -ms
docid027110 rev 2 21/114 VX6854LC functional description 69 figure 7. VX6854LC power-up sequence for ccp2 mode t0 t1 t3 t4 t5 t6 vdig vana xshutdown extclk (gated) sda scl clkp/- datap/- frame count register extclk may be free running or gated read device id configure device enter streaming high z (tri-state) 0xff 0x00 high z (tri-state) t2 t7 power-off hw- sw-standby streaming this is an example of vana rising after vdig standby extclk (free running)
functional description VX6854LC 22/114 docid027110 rev 2 figure 8. VX6854LC power-up sequence for csi-2 mode t5 t6 extclk (free running) sda scl clkp/- datap/- frame count register extclk may be free running or gated read device id configure device enter streaming 0xff 0x00 t7 streaming low power low power high-speed tx t0 t1 t3 vdig or vana vana or vdig xshutdown t2 power-off hw- sw-standby standby this is an example of vana rising after vdig t4 extclk (gated)
docid027110 rev 2 23/114 VX6854LC functional description 69 3.4.2 power-down procedure table 9. power-down sequence timing constraints for csi2 communications symbol parameter min. max. units t8 last i 2 c transaction to mipi frame end (1) 1. the whole power down sequence is triggered by the cci power down request, however the power down sequence will only start after the end of the fr ame when all active data are consumed on csi-2 dn/dp pins. when this is done, the csi-2 dn/dp signals enter lp11. the csi-2 clock will enter lp11 with a delay of 5us (corresponding to tclk_post + tclk_trail ) compared to dn/dp pins. the device is then sw_standby and will enter lp00 and stay in ultra low power mode. - 1 frame t9 minimum extclk cycles required after last i 2 c transaction or mipi frame end (2) 2. after the last frame completion, the gated clock needs to be kept for 512 cycles at least so the system can enter ultra low power state. after the system enters ulps mode, you can keep or stop the extclk. 512 - clock cycles t10 last i 2 c transaction or mipi frame end to xshutdown failling (3) 3. note: xshutdown can be asserted at any time. this immediately removes the core-supply, causing the por to trigger and reset all the digital logic and macros - it does not depend on the presence of the clock. when xshutdown is asserted, the clock can be running or not - it does not matter. t8+t9 - t11 xshutdown to vana/vdig falling xshutdown must fall at the same time as, or earlier than, both power supplies (vdig and vana) t12 vana to vdig or vdig to vana falling vana and vdig may fall in any order, the rising separation can vary from 0 ns to indefinite
functional description VX6854LC 24/114 docid027110 rev 2 figure 9. VX6854LC power-down sequence for csi-2 mode extclk (free running) extclk (gated) sda scl clkp/- datap/- extclk may be free running or gated configure device t8 streaming lp11 high-speed tx t12 t11 vdig xshutdown power-off hw- standby high-speed tx stop streaming t9 vana sw_standby this is an example of vana falling after vdig lp11 t10 ulps ulps ulps ulps undefined (power is off) undefined (power is off) lp00 lp00
docid027110 rev 2 25/114 VX6854LC functional description 69 3.4.3 internal power-on reset (por) the VX6854LC internally performs a power- on reset (por) when the 1v2 vcore digital supply rises through the trigger level, vtrig_rising. similarly, if the 1v2 vcore digital power supply falls through the trigger level, vtrig_falling, then the power-on reset will also trigger. definitions: figure 10. por timing rise threshold voltage (vtrigr) this is the su pply voltage level that is recognised by the por as voltage ?high?. only after the supply reaches this level does the output of por change to high level if it is off, after a specified amount of delay. fall threshold voltage (vtrigf) this is the supp ly voltage level that is recognised by the por as voltage ?low?. only after the supply reaches this level does the output of por change to low (ground) level if it is on. burst width (pw) burst is the negative pulse riding the supply signal. the burst width is measured as the amount of duration for which the supply signal dropped beyond the threshold levels. delay duration (tpor) delay duration is defined as the time duration for which por stays off before re-powering. each reset of por will impart a specified dela y duration before por re- powers. table 10. por cell characteristics symbol constraint min typ. max units vtrigr por rise voltage detection - - 0.95 v vtrigf por fall voltage detection 0.4 - - v tburst (pw) burst filter - 2 8 s tpor delay duration - 20 45 s
functional description VX6854LC 26/114 docid027110 rev 2 3.4.4 failsafe signals all signals going into the VX6854LC must be either at a low state or high impedance when power is removed from the device. the exceptions to this rule are the extclk, xshutdown and the cci signals. these pads have been designed to be high impedance when the VX6854LC is powered- down. this means that the input signal on the specified pads can either be high or low with no leakage problems. 3.5 clock and frame rate timing 3.5.1 video frame rate control the output frame rate of VX6854LC can be reduced by extending either the line length or the frame length. the extension is achieved by adding extra blanking bytes at the end of a line or ?blank? video lines to act as timing padding. the frame rate can be reduced from the default 20 frame/s at 3.15 mpixel resolution to less than 3 frame/s at 3.15 mpixel resolution. the advantage of the frame extension approach is that it does not reduce the pixel readout rate or the active frame time and therefore does not introduce unwante d motion distribution effects to the image. 3.5.2 pll and clock input the VX6854LC has an embedded pll block. this block generates all necessary internal clocks from an input range defined in table 11 . the input clock pad accepts sine wave or square wave. table 11. system input clock frequency range minimum (mhz) maximum (mhz) 6 27
docid027110 rev 2 27/114 VX6854LC functional description 69 3.5.3 clock input type as required by the smia specification the VX6854LC can receive the clock types shown in figure 11 . note that the extclk pad has a schmitt trigger input. figure 11. clock input types the clock is fail-safe/high impedance when in either ac or dc coupled and in any mode including the power off state. pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor pad pad extclk extclk camera module host processor 1st option dc-coupled 2nd option ac-coupled 3rd option dc-coupled 4th option ac-coupled and filtered and filtered pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn pwrdn
functional description VX6854LC 28/114 docid027110 rev 2 3.6 control and video interface formats image data is transferred from the VX6854LC using a high speed sublvds serial link.the serial control data is tr ansferred to and from the VX6854LC using a cci bus. 3.6.1 ccp/csi-2 serial data link data signals (data+ and data-) and clock signals (clk+ and clk-) are transferred from VX6854LC using two pairs of balanced 100 impedance transmission lines. the transmission line pairs and custom transmitters/receivers realize a very low voltage differential (sublvds) signalling scheme that can transfer inform ation in a potentially noisy environment. as implemented in VX6854LC, the ccp link sup ports the transmission of raw bayer data at 3.15 mpixel resolution up to 20 frame/s at 8-bit or 10-8 bit compressed resolution or 15 frame/s at 10-bit resolution. as implemented in VX6854LC, the csi-2 link supports the transmission of raw bayer data at 3.15 mpixel resolution up to 20 frame/s at 10-bit resolution. 3.6.2 cci serial control bus the internal registers in VX6854LC can be co nfigured by a master device using a cci bus (sda, scl). VX6854LC sends and receives commands over this bus at up to 400 kbit/s. the cci bus uses a device address of 0x20 for writes and 0x21 for reads.
docid027110 rev 2 29/114 VX6854LC register map 69 4 register map 4.1 status registers [0x0000 to 0x000f] table 12. status registers [0x0000 to 0x000f] index byte register name data type default type comment 0x0000 hi model_id 16ui 03.56 ro camera model identifcation 0x0356 = 854 10 (this value is derived from the nvm) 0x0001 lo 0x0002 revision_number_major 8ui 02 ro revision identifier of the camera for dcc change 00: unprogrammed 01: es1.0 02: es2.0 (this value is derived from the nvm) 0x0003 manufacturer_id 8c 01 ro module manufacturer id: st (this value is derived from the nvm) 0x0004 smia_version 8c 0a ro 0x0a: smia 1.0 0x0005 frame_count 8ui ff ro frame count increments by 1 on each frame. rolls over at 255 to 0. when moving from video to sleep the frame count will be reset to 255. the frame count will also be reset to 255 after a soft reset (register 0x0103). 0x0006 pixel_order 8c 00 ro color pixel readout order. defines the order of the colour pixel readout. changes with mirror and flip (register 0x0101). 0x00 - gr/bg - normal 0x01 - rg/gb - horizontal mirror 0x02 - bg/gr - vertical flip 0x03 - gb/rg - vertical flip and horizontal mirror 0x0008 hi data_pedestal 16ui 00.40 ro the video data is offset by 64. 0x0009 lo 0x000c pixel_depth 8ui 0a ro pixel data resolution. 0x0010 revision_number_minor 8ui 00 ro revision identifier of the camera for minor changes (this value is derived from the nvm) 0x0011 additional_spec_ver 8ui 06 ro additional specification identifier 0x0012 module_date_year 8ui 00 ro manufacturing year (this value is derived from the nvm) 0x0013 module_date_month 8ui 00 ro manufacturing month (this value is derived from the nvm)
register map VX6854LC 30/114 docid027110 rev 2 0x0014 module_date_day 8ui 00 ro manufacturing day (this value is derived from the nvm) 0x0015 module_date_phase 8ui 01 ro manufacturing phas e identification 00: ts 01: es 02: cs 03: mp (this value is derived from the nvm) 0x0016 hi sensor_model_id 16ui 03.56 ro silicon identification 0x0356 = 854 10 0x0017 lo 0x0018 sensor_revision_number 8ui 30 ro bits 3:0 nvm version bits 7:4 silicon mask revsion 00: cut1.0 10: cut1.1 20: cut2.0 30: cut2.1 40: cut2.2 (the value for bits[3:0] is derived from the nvm) 0x0019 sensor_manufacturer_id 8c 01 ro silicon manufacturer id:st 0x001a sensor_firmware_ver 8c 30 ro silicon firmware version 0x001c hi serial_number 32ui 00.00 00.00 ro serial number (this value is derived from the nvm) 0x001d 0x001e 0x001f lo table 12. status registers [0x0000 to 0x000f] (continued) index byte register name data type default type comment
docid027110 rev 2 31/114 VX6854LC register map 69 4.2 frame format description registers [0x0 040 to 0x007f] for a full description of the frame format description refer to chapter 5: video data interface on page 52 . 4.3 analogue gain descriptio n registers [0x0080 to 0x0097] these registers are not dynamic but are required to be output on the status line so that it is possible to interpret the meaning of the analogue gain code(s). for a full description of the analogue gain description registers refer to section 6.5.1: analogue gain model on page 67 . table 13. frame format description registers [0x0040 to 0x007f] index byte register name data type default type comment 0x0040 frame_format_model_type 8c 01 ro generic frame format. 0x01: 2-byte data format. (1) 0x0041 frame_format_model_subtype 8c 12 ro contains the number of 2-byte data format descriptors used. upper nibble defines the number of column descriptors i.e 1. the lower nibble defines the number of row descriptors i.e. 2 0x0042 hi frame_format_descriptor_0 16c 58.10 ro pixel data code: 5 (visible columns) number of pixels : readout dependent (maximum of 2064) 0x0043 lo 0x0044 hi frame_format_descriptor_1 16c 10.02 ro pixel data code: 1 (embedded data lines) number of lines: 2 0x0045 lo 0x0046 hi frame_format_descriptor_2 16c 56.10 ro pixel data code: 5(visible lines) number of lines: readout dependent(maximum of 1552) 0x0047 lo 1. see section 4.5 of smia 1.0 functional specification. table 14. analogue gain description [0x0080 to 0x0097] index byte register name data type default type comment 0x0080 hi analogue_gain_capability 16b 00.00 ro analogue gain capability 0 ? single global analogue gain only 0x0081 lo 0x0084 hi analogue_gain_code_min 16ui 00.00 ro minimum recommended analogue gain code that is, 0 (x1 gain) 0x0085 lo 0x0086 hi analogue_gain_code_max 16ui 00.f0 ro maximum recommended analogue gain code that is, 240 (x16 gain) 0x0087 lo 0x0088 hi analogue_gain_code_step 16ui 00.10 ro analogue gain code step size (1) 0x0089 lo
register map VX6854LC 32/114 docid027110 rev 2 4.4 data format description registers [0x00c 0 to 0x00ff] the data format description registers specify which ccp data formats the smia camera module supports. specifically VX6854LC supports ccp raw 8, 10-8 compressed and raw10. 0x008a hi analogue_gain_type 16ui 00.00 ro analogue gain type 0x008b lo 0x008c hi analogue_gain_m0 16si 00.00 ro analogue gain m0 constant. m0 = 0 0x008d lo 0x008e hi analogue_gain_c0 16si 01.00 ro analogue gain c0 constant. c0 = 256 0x008f lo 0x0090 hi analogue_gain_m1 16si ff.ff ro analogue gain m1 constant. m1 =-1 0x0091 lo 0x0092 hi analogue_gain_c1 16si 01.00 ro analogue gain c1 constant c1 = 256 0x0093 lo 1. for above gains of 0xe0, the step size is four. see figure 26 on page 68 for gain values. this additional feature of the VX6854LC is outside of the smia specification. table 14. analogue gain description [0x0080 to 0x0097] (continued) index byte register name data type default type comment table 15. data format description registers [0x00c0 to 0x00ff] index byte register name data type default type comment 0x00c0 data_format_model_type 8ui 01 ro 2-byte generic data format model. always 0x01 0x00c1 data_format_model_subtype 8ui 03 ro number of descriptors i.e. 3 0x00c2 hi data_format_descriptor_0 16ui 08.08 ro top 8-bits of internal pixel data transmitted as raw 8. 0x00c3 lo 0x00c4 hi data_format_descriptor_1 16ui 0a.0a ro top 10-bits of internal pixel data transmitted as raw 10. 0x00c5 lo 0x00c6 hi data_format_descriptor_2 16ui 0a.08 ro compress top 10-bits of internal pixel data to 8. transmitted as raw 8 mode. 0x00c7 lo
docid027110 rev 2 33/114 VX6854LC register map 69 4.5 setup registers [0x0100 to 0x01ff] table 16. setup registers [0x0100 to 0x01ff] index byte register name data type default type comment 0x0100 mode_select 8ui 00 rw mode select 0x00 - software standby 0x01 - streaming refer to section 3.3: device operating modes on page 18 0x0101 image_orientation 8b 00 rw image orientation i.e. horizontal mirror and vertical flip. bit 0: 0 - no mirror, 1 - horizontal mirror enable bit 1: 0 - no flip, 1 - vertical flip enable 0x0103 software_reset 8ui 00 rw software reset. settin g this register to 1 resets the sensor to its power up defaults. the value of this bit is also reset 0x00 - normal 0x01 - soft reset refer to section 3.3: device operating modes on page 18 a 2.2ms delay is required after issuing the software reset command (6mhz clock) 0x0104 grouped_parameter_hold 8ui 00 rw the grouped parameter hold register disables the consumption of integration, gain and video timing parameters 0x00 - consume parameters as normal 0x01 - hold parameters refer to section 6.5.3: integration and gain parameter re-timing on page 69 0x0105 mask_corrupted_frames 8ui 00 rw setting this register to 1 prevents the sensor out-putting frames that have been corrupted by video timing parameter changes. 0x00 - normal 0x01 - mask corrupted frames 0x0110 csi_channel_identifier 8ui 00 rw the dma (ccp2) or virtual (csi2) channel identifier. 0x0111 csi_signalling_mode 8ui 02 rw 0x00 - ccp2 data/clock signalling 0x01 - ccp2 data/strobe signalling 0x02 - csi-2 this register should not be changed while the device is streaming data.
register map VX6854LC 34/114 docid027110 rev 2 4.6 integration time and gain registers [0x0 200 to 0x02ff] these registers are used to control the image exposure. see section 6.5: exposure and gain control on page 67 for more information. 0x0112 hi csi_data_format 16ui 0a.0a rw the msb contains the bit width of the uncompressed pixel data. the lsb contains the bit width of the compressed pixel data. 0a.0a - raw10 mode 0a.08 - 10-8 compressed mode 08.08 - raw8 mode 0x0113 lo 0x0114 csi_lane_mode 8ui 00 rw number of data lanes in use 00 - 1-lane 0x0120 gain_mode 8ui 00 ro 0x00 ? global analogue gain. VX6854LC supports only global gain modes. 0x0136 hi ext_clock_freq 8.8ur 06.00 rw frequency of external crystal 0x0137 lo table 16. setup registers [0x0100 to 0x01ff] (continued) index byte register name data type default type comment table 17. integration time and gain registers [0x0200 to 0x02ff] index byte register name data type default type comment 0x0200 hi fine_integration_time 16u i 01.e5 rw fine integration time (pixels). 0x0201 lo 0x0202 hi coarse_integration_time 16ui 00.00 rw c oarse integration time (lines). 0x0203 lo 0x0204 hi analogue_gain_code_global 16ui 00.00 rw global analogue gain parameter (coded). see section 6.5.1: analogue gain model on page 67 for details of how to use this parameter. 0x0205 lo 0x020e hi digital_gain_greenr 16ur 01.00 rw gain code for greenr channel 0x020f lo 0x0210 hi digital_gain_red 16ur 01.00 rw gain code for red channel 0x0211 lo 0x0212 hi digital_gain_blue 16ur 01.00 rw gain code for blue channel 0x0213 lo 0x0214 hi digital_gain_greenb 16ur 01.00 rw gain code for greenb channel 0x0215 lo
docid027110 rev 2 35/114 VX6854LC register map 69 4.7 video timing regi sters [0x0300 to 0x03ff] for a full description of the video timing registers refer to chapter 6: video timing on page 55 . table 18. video timing registers [0x0300 to 0x03ff] index byte register name data type default type comment 0x0300 hi vt_pix_clk_div 16ui 00.0a rw number of system clocks per pixel clock. 0x0301 lo 0x0302 hi vt_sys_clk_div 16ui 00.01 rw s ystem clock divider value 0x0303 lo 0x0304 hi pre_pll_clk_div 16ui 00.01 rw pre pll clock divider value 0x0305 lo 0x0306 hi pll_multiplier 16ui 00.85 rw pll multiplier value value:133 0x0307 lo 0x0308 hi op_pix_clk_div 16ui 00.0a rw number of output system clocks per pixel clock. 0x0309 lo 0x030a hi op_sys_clk_div 16ui 00.01 rw output system clock divider value 0x030b lo 0x0340 hi frame_length_lines 16ui 06.40 rw frame length value:1600 units: lines 0x0341 lo 0x0342 hi line_length_pck 16ui 09.c4 rw line length value:2500 units: pixel clocks 0x0343 lo 0x0344 hi x_addr_start 16ui 00.00 rw x-address of the top left corner of the visible pixel data units: pixels 0x0345 lo 0x0346 hi y_addr_start 16ui 00.00 rw y-address of the top left corner of the visible pixel data (1) units: lines 0x0347 lo 0x0348 hi x_addr_end 16ui 08.0f rw x-address of the bottom right corner of the visible pixel data units: pixels 0x0349 lo 0x034a hi y_addr_end 16ui 06.0f rw y-address of the bott om right corner of the visible pixel data units: lines 0x034b lo 0x034c hi x_output_size 16ui 08.10 rw width of image data output from the sensor module units: pixels 0x034d lo
register map VX6854LC 36/114 docid027110 rev 2 4.8 image scaling regi sters [0x0400 to 0x04ff] 0x034e hi y_output_size 16ui 06.10 rw height of image data output from the sensor module units: lines 0x034f lo 0x0380 hi x_even_inc 16ui 00.01 rw increment for even pixels. x_even_inc must = 1 for focu s_estimation to operate effectively. units: pixels 0x0381 lo 0x0382 hi x_odd_inc 16ui 00.01 rw increment for odd pixels units: pixels 0x0383 lo 0x0384 hi y_even_inc 16ui 00.01 rw increment for even pixels. y_even_inc must = 1 for focu s_estimation to operate effectively. VX6854LC only suppports y-even-inc values of 1 and 5 units: pixels 0x0385 lo 0x0386 hi y_odd_inc 16ui 00.01 rw increment for odd pixels units: pixels 0x0387 lo 1. has to be modulo 4 for correct operation of device table 18. video timing registers [0x0300 to 0x03ff] (continued) index byte register name data type default type comment table 19. image scaling registers [0x0400 to 0x04ff] index byte register name data type default type comment 0x0400 hi scaling_mode 16ui 00.00 rw 0 ? no scaling 1 ? horizontal scaling. 2 - full scaling (horizontal and vertical). 0x0401 lo 0x0402 hi spatial_sampling 16ui 00.00 rw 0 ? bayer sampling 1 ? co-sited sampling 0x0403 lo 0x0404 hi scale_m 16ui 00.10 rw down scale factor m component. (denominator) 0x0405 lo 0x0406 hi scale_n 16ui 00.10 ro down scale factor n component. (numerator, always 16) 0x0407 lo
docid027110 rev 2 37/114 VX6854LC register map 69 4.9 image compression re gisters [0x0500 to 0x05ff] 4.10 test pattern regi sters [0x0600 to 0x06ff] table 20. image compression registers [0x0500 to 0x05ff] index byte register name data type default type comment 0x0500 hi compression_mode 16ui 00.01 ro 1 ? dpcm/pcm compression (simple predictor) 0x0501 lo table 21. test pattern registers [0x0600 to 0x06ff] index byte register name data type default type comment 0x0600 hi test_pattern_mode 16c 00.00 rw 0 ? normal operation (default) 1 ? solid colour bars (1) 2 ? 100% colour bars (1) 3 ? fade to grey? color bars (1) 4 ? pn9 (2) 5 to 255 - reserved 0x0601 lo 0x0602 hi test_data_red 16ui 00.00 rw the test data used to replace red pixel data. range 0 to 1023. (3) 0x0603 lo 0x0604 hi test_data_greenr 16ui 00.00 rw the test data used to replace green pixel data on rows that also have red pixels. valid range 0 to 1023. (1) 0x0605 lo 0x0606 hi test_data_blue 16ui 00.00 rw the test data used to replace blue pixel data. range 0 to 1023 (1) 0x0607 lo 0x0608 hi test_data_greenb 16ui 00.00 rw the test data used to replace green pixel data on rows that also have blue pixels. range 0 to 1023 (1) . 0x0609 lo 0x060a hi horizontal_cursor_width 16ui 00.00 rw defines the width of the horizontal cursor (in pixels). 0x060b lo 0x060c hi horizontal_cursor_position 16ui 00.00 rw defines the top edge of the horizontal cursor. 0x060d lo 0x060e hi vertical_cursor_width 16ui 00.00 rw defines the width of the vertical cursor (in pixels). 0x060f lo 0x0610 hi vertical_cursor_position 16ui 00.00 rw defines the left hand edge of the vertical cursor. a value of 0x0fff switches the vertical cursor into automatic mode wher e it automatically advances every frame. 0x0611 lo 1. on cut2.x silicon, the pedestal value of 64d will be added to the pixel value. to disable the pedestal, set 0x31d0= 00, 0x31e8=0, 0x3120=0x00. (the lens shadi ng block must also be disabled). 2. this mode must be entered and exited via software standby. the embedded data lines will also be output. 3. some clipping of these values may occur to prevent false sync codes being generated
register map VX6854LC 38/114 docid027110 rev 2 4.11 fifo water mark re gisters [0x0700 to 0x0701] 4.12 dphy registers [0x0810 to 0x0811] 4.13 binning registers [0x0900 to 0x0902] table 22. fifo water mark registers [0x0700 to 0x0701] index byte register name data type default type comment 0x0700 hi fifo_water_mark_pixels 16ui 00.28 rw the level at which data starts to be transmitted out of t he fifo (default = 40) 0x0701 lo table 23. dphy registers [0x0810 to 0x0811] index byte register name data type default type comment 0x0820 hi dphy_channel_mbps_for_ui 32ui 00.00 rw csi-2 dphy channel in mbps (16.16 fixed point) this is used by the dphy to calculate ui(unit interval) value. it does not control the sensor clock set-up, but should normally correspond to those settings. 0: sensor automatica lly calculates ui from the op_sys_clk_freq_mhz value. 80-800: sensor calcul ates ui from this value. 0x0821 3rd 0x0822 2nd 0x0823 lo table 24. binning registers [0x0900 to 0x0902] index byte register name data type default type comment 0x0900 binning_mode 8ui 00 rw binning mode 0 - disabled 1 - enabled 0x0901 binning_type 8ui 00 rw high-nibble - column binning factor low-nibble - row binning factor 0x0902 binning_weighting 8ui 00 rw bit0: averaged (1-enable) bit2: bayer corrected (1-enable)
docid027110 rev 2 39/114 VX6854LC register map 69 4.14 data transfer registe rs [0x0a00 to 0x0a02] 4.15 shading correction regi sters [0x0b00 to 0x0b00] table 25. data transfer registers [0x0a00 to 0x0a02] index byte register name data type default type comment 0x0a00 if1_ctrl 8ui 00 rw bit0: 0 - if1 transfer disabled 1 - if1 transfer enabled bit1: 0 - if1 read enabled 1 - if1 write enabled bit2: 0 - normal operation 1 - clear error bits on if1 0x0a01 if1_status 8ui 00 rw bit0: read interface ready bit1: write interface ready bit2: data corrupt bit3: improper interface uage 0x0a02 if1_page_sel 8ui 00 rw select page for if1: page 00: nvm: 0xfc00 - 0xfc3f page 01: nvm: 0xfc40 - 0xfc7f page 02: nvm: 0xfc80 - 0xfcbf page 03: nvm: 0xfcc0 - 0xfcff page 04: nvm: 0xfd00 - 0xfd3f page 05: nvm: 0xfd40 - 0xfd7f page 06: nvm: 0xfd80 - 0xfdbf page 07: nvm: 0xfdc0 - 0xfdff table 26. shading correction registers [0x0b00 to 0x0b00] index byte register name data type default type comment 0x0b00 shading_correction_enable 8ui 01 rw shading correction 0 - disable 1 - enable
register map VX6854LC 40/114 docid027110 rev 2 4.16 defect correction regi sters [0x0b05 to 0x0b09] 4.17 edof registers [0x0b80 to 0x0b8a] table 27. defect correction registers [0x0b05 to 0x0b09] index byte register name data type default type comment 0x0b05 mapped_couplet_correct_ena ble 8ui 01 rw mapped couplet correction 0 - disable 1 - enable 0x0b06 single_defect_correct_enable 8ui 01 rw single defect correction 0 - disable 1 - enable 0x0b07 single_defect_correct_weight 8ui 40 rw single defect correction weight 1-127 manual mode bit[7]=1 auto, weight varies with analog gain 0x0b08 dynamic_couplet_correct_ena ble 8ui 00 rw dynamic couplet correction 0 - disable 1 - enable (note: if enabled, the single defect correction will also be enabled). 0x0b09 dynamic_couplet_correct_wei ght 8ui 00 rw not used in VX6854LC table 28. edof registers [0x0b80 to 0x0b8a] index byte register name data type default type comment 0x0b80 edof_mode 8ui 00 rw edof control 0 - edof disabled (power saving) 1 - edof application (capture) 2 - edof estimation (preview) 0x0b81 edof_est_depth_of_field 8ui 00 ro not used in VX6854LC 0x0b82 edof_est_focus_distance 8ui 32 ro the estimated focus point (cm) 0x0b83 edof_sharpness 8ui 00 rw edof sharpness control 1-127 - manual mode 128-255 - signed offset added to internal default value. 0x0b84 edof_denoising 8ui 00 rw edof denoising control 1-127 - manual mode 128-255 - signed offset added to internal default value.
docid027110 rev 2 41/114 VX6854LC register map 69 4.18 color feedback regist ers [0x0b8c to 0x0b95] 0x0b85 edof_module_specific 8ui 00 rw edof noise vs. details control 1-127 - manual mode 128-255 - signed offset added to internal default value. 0x0b88 hi edof_focus_distance 16ui 00.32 rw value supplied by the host which is used by VX6854LC for focus distance. (in cm) 0x0000 to 0x7fff - manual mode 0x8000 to 0xffff - auto mode 0x0b89 lo 0x0b8a edof_estimation_control 8ui 00 rw edof estimator control 0 - uniform 1 - uniform 2 - centre weight 4 - large spot 8 - narrow spot table 28. edof registers [0x0b80 to 0x0b8a] (continued) index byte register name data type default type comment table 29. color feedback registers [0x0b8c to 0x0b95] index byte register name data type default type comment 0x0b8c hi colour_temperature 16sr 00.00 rw not supported by VX6854LC 0x0b8d lo 0x0b8e hi host_wb_stats_green_red 16ur 01.00 rw white balance gains to be applied by the host. these stats are used by the edof and the adaptive av to estimate the color temperature of the scene. 0x0b8f lo 0x0b90 hi host_wb_stats_red 16ur 01.00 rw 0x0b91 lo 0x0b92 hi host_wb_stats_blue 16ur 01.00 rw 0x0b93 lo 0x0b94 hi host_wb_stats_green_blue 16ur 01.00 rw 0x0b95 lo
register map VX6854LC 42/114 docid027110 rev 2 4.19 integration time and gain pa rameter limit regi sters [0x1000 to 0x10ff] these registers are used to define exposure limits for the integrat ion control registers (0x200 to 0x203). see section 6.5: exposure and gain control on page 67 for more information. table 30. integration time and gain parameter limit registers [0x1000 to 0x10ff] index byte register name data type default type comment 0x1000 hi integration_time_capability 16ui 00.01 ro 0x0001 ? coarse and smooth (1 pixel) fine integration. 0x1001 lo 0x1004 hi coarse_integration_t ime_min 16ui 00.00 ro minimum coarse integration time. line periods. 0x1005 lo 0x1006 hi coarse_integr ation_time_max _margin 16ui 00.09 ro current frame length ? current max coarse exposure. line periods. 0x1007 lo 0x1008 hi fine_integration_tim e_min 16ui 01.e5 ro minimum fine integration time. pixel periods. 0x1009 lo 0x100a hi fine_integratio n_time_max_ margin 16ui 07.73 ro current line length ? current max fine exposure. pixel periods. 0x100b lo 0x1080 hi digital_gain_capability 16ui 00.01 ro 0x01 ? supports digital gain. 0x1081 lo 0x1084 hi digital_gain_min 16ur 00.08 ro 1.00000 minimum 0x1085 lo 0x1086 hi digital_gain_max 16ur 01.f8 ro 1.96875 maximum 0x1087 lo 0x1088 hi digital_gain_step_size 16ur 00.08 ro 0.03125 step size 0x1089 lo
docid027110 rev 2 43/114 VX6854LC register map 69 4.20 video timing parameter limi t registers [0x1100 to 0x11ff] for a full description of the video timi ng parameter limit registers refer to chapter 6: video timing on page 55 . table 31. video timing parameter li mit registers [0x1100 to 0x11ff] index byte register name data type default type comment 0x1100 hi min_ext_clk_freq_mhz 32sf 40.c0 00.00 ro minimum external clock frequency units: mhz value: 6.0 0x1101 3rd 0x1102 2nd 0x1103 lo 0x1104 hi max_ext_clk_freq_mhz 32sf 41.d8 00.00 ro maximum external clock frequency units: mhz value: 27.0 0x1105 3rd 0x1106 2nd 0x1107 lo 0x1108 hi min_pre_pll_clk_div 16ui 00.01 ro minimum pre pll divider value value: 1 0x1109 lo 0x110a hi max_pre_pll_clk_div 16ui 00.04 ro maximum pre pll divider value value: 4 0x110b lo 0x110c hi min_pll_ip_freq_mhz 32sf 40.c0 00.00 ro minimum pll input clock frequency units: mhz value: 6.0 0x110d 3rd 0x110e 2nd 0x110f lo 0x1110 hi max_pll_ip_freq_mhz 32sf 41.40 00.00 ro maximum pll input clock frequency units: mhz value: 12.0 0x1111 3rd 0x1112 2nd 0x1113 lo 0x1114 hi min_pll_multiplier 16ui 00.25 ro minimum pll multiplier value: 37 0x1115 lo 0x1116 hi max_pll_multiplier 16ui 00.86 ro maximum pll multiplier value: 134 0x1117 lo 0x1118 hi min_pll_op_freq_mhz 32sf 43.e1 00.00 ro minimum pll output clock frequency units: mhz value: 450.0 0x1119 3rd 0x111a 2nd 0x111b lo
register map VX6854LC 44/114 docid027110 rev 2 0x111c hi max_pll_op_freq_mhz 32sf 44.7a 00.00 ro maximum pll output clock frequency units: mhz value: 1000.0 note: this value should be 800mhz 0x111d 3rd 0x111e 2nd 0x111f lo 0x1120 hi min_vt_sys_clk_di v 16ui 00.01 ro minimum video-timing system clock divider value value: 1 0x1121 lo 0x1122 hi max_vt_sys_clk_div 16ui 00.04 ro maximum video-timing system clock divider value value: 4 this value should be 2. 0x1123 lo 0x1124 hi min_vt_sys_clk_freq_mhz 32sf 42.f4 00.00 ro minimum video-timing system clock frequency units: mhz value: 122.0 0x1125 3rd 0x1126 2nd 0x1127 lo 0x1128 hi max_vt_sys_clk_freq_mhz 32sf 44.48 00.00 ro maximum video-timing system clock frequency units: mhz value: 800.0 0x1129 3rd 0x112a 2nd 0x112b lo 0x112c hi min_vt_pix_clk_freq_mhz 32sf 42.18 00.00 ro minimum video-timing pixel clock frequency units: mhz value: 38.0 0x112d 3rd 0x112e 2nd 0x112f lo 0x1130 hi max_vt_pix_clk_freq_mhz 32sf 42.a0 00.00 ro maximum video-timing pixel clock frequency units: mhz value: 80.0 0x1131 3rd 0x1132 2nd 0x1133 lo 0x1134 hi min_vt_pix_clk_div 16ui 00.04 ro minimum video-timing pixel clock divider value: 4 0x1135 lo 0x1136 hi max_vt_pix_clk_div 16ui 00.0a ro maximum video-timing pixel clock divider value: 10 0x1137 lo 0x1140 hi min_frame_length_lines 16ui 00.2a ro minimum frame length allowed. value = 42 lines 0x1141 lo table 31. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment
docid027110 rev 2 45/114 VX6854LC register map 69 0x1142 hi max_frame_length_lines 16ui ff.ff ro maximum possible number of lines per frame. value = 65535 units: lines 0x1143 lo 0x1144 hi min_line_length_pck 16ui 09.c4 ro minimum line length allowed. value = 2500 units: pixel clocks 0x1145 lo 0x1146 hi max_line_length_pck 16ui 3f.ff ro maximum possible number of pixel clocks per line. value = 16383 units: pixel clocks 0x1147 lo 0x1148 hi min_line_blanking_pck 16ui 01.a8 ro minimum line blanking time in pixel clocks value = 424 units: pixel clocks 0x1149 lo 0x114a hi min_frame_blanking_lines 16ui 00.24 ro minimum frame blanking in video lines = 36 0x114b lo 0x1160 hi min_op_sys_clk_div 16ui 00.01 ro minimum output system clock divider. value = 1 0x1161 lo 0x1162 hi max_op_sys_clk_div 16ui 00.42 ro maximum output system clock divider value = 66 0x1163 lo 0x1164 hi min_op_sys_clk_freq_mhz 32sf 40.f2 6c.9b ro minimum output system clock frequency units: mhz value: 7.57 note that this value is 80mhz in csi2 mode. 0x1165 0x1166 0x1167 lo 0x1168 hi max_op_sys_clk_freq_mhz 32sf 44.48 00.00 ro maximum output system clock frequency units: mhz value: 800.0 0x1169 0x116a 0x116b lo 0x116c hi min_op_pix_clk_div 16ui 00.08 ro minimum output pixel clock divider. value = 8 0x116d lo 0x116e hi max_op_pix_clk_div 16ui 00.0a ro maximum output pixel clock divider value = 10 0x116f lo 0x1170 hi min_op_pix_clk_freq_mhz 32sf 3f.41 f0.7c ro minimum output pixel clock frequency units: mhz value: 0.757 (757 khz) 0x1171 0x1172 0x1173 lo table 31. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment
register map VX6854LC 46/114 docid027110 rev 2 0x1174 hi max_op_pix_clk_freq_mhz 32sf 42.a0 00.00 ro maximum output pixel clock frequency units: mhz value: 80.0 0x1175 0x1176 0x1177 lo 0x1180 hi x_addr_min 16ui 00.00 ro minimum x-address of the addressable pixel array value: always 0 0x1181 lo 0x1182 hi y_addr_min 16ui 00.00 ro minimum y-address of the addressable pixel array value: always 0 0x1183 lo 0x1184 hi x_addr_max 16ui 08.0f ro maximum x-address of the addressable pixel array value = 2063 0x1185 lo 0x1186 hi y_addr_max 16ui 06.0f ro maximum y-address of the addressable pixel array value = 1551 0x1187 lo 0x1188 hi min_x_output_size 16ui 01.00 ro minimum x output size in pixels. value: 256 0x1189 lo 0x118a hi min_y_output_size 16ui 00.04 ro minimum y output size in pixels. value: 4 0x118b lo 0x118c hi max_x_output_size 16ui 08.10 ro maximum x output size in pixels. value: 2064 0x118d lo 0x118e hi max_y_output_size 16ui 06.10 ro maximum y output size in pixels: value: 1552 0x118f lo 0x11c0 hi min_even_inc 16ui 00.01 ro minimum increment for even pixels 0x11c1 lo 0x11c2 hi max_even_inc 16ui 00.07 ro maximum increment for even pixels. even_inc must = 1 for focus_estimation to operate effectively. VX6854LC only suppports y-even-inc values of 1 and 5 0x11c3 lo 0x11c4 hi min_odd_inc 16ui 00.01 ro minimum increment for odd pixels 0x11c5 lo 0x11c6 hi max_odd_inc 16ui 00.07 ro maximum increment for odd pixels 0x11c7 lo table 31. video timing parameter limit registers [0x1100 to 0x11ff] (continued) index byte register name data type default type comment
docid027110 rev 2 47/114 VX6854LC register map 69 4.21 image scaling parameter limit registers [0x1200 to 0x12ff] 4.22 image compression paramete r registers [0x1 300 to 0x13ff] 4.23 color matrix regist ers [0x1400 to 0x14ff] table 32. image scaling parameter limit registers [0x1200 to 0x12ff] index byte register name data type default type comment 0x1200 hi scaling_capablility 16ui 00.02 ro VX6854LC supports full (horizontal & vertical) scaling. 0x1201 lo 0x1204 hi scale_m_min 16ui 00.10 ro down scale factor: minimum m value = 16 0x1205 lo 0x1206 hi scale_m_max 16ui 00.81 ro down scale factor: maximum m value = 129 0x1207 lo 0x1208 hi scale_n_min 16ui 00.10 ro down scale factor: minimum n value = 16 0x1209 lo 0x120a hi scale_n_max 16ui 00.10 ro down scale factor: maximum n value = 16 0x120b lo table 33. image compression parameter limit registers [0x1300 to 0x13ff] index byte register name data type default type comment 0x1300 hi compression_capablility 16ui 00.01 ro VX6854LC supports dpcm/pcm compression 0x1301 lo table 34. color matrix registers [0x1400 to 0x14ff] index byte register name data type default type comment 0x1400 hi matrix_element_redinred 16sr 01.00 ro color matrix parameter for red in red 0x1401 lo 0x1402 hi matrix_element_greeninred 16sr 00.00 ro color matrix parameter for green in red 0x1403 lo 0x1404 hi matrix_element_blueinred 16sr 00.00 ro color matrix parameter for blue in red 0x1405 lo 0x1406 hi matrix_element_redingreen 16sr 00.00 ro color matrix parameter for red in green 0x1407 lo 0x1408 hi matrix_element_greeningreen 16sr 01.00 ro color matrix parameter for green in green 0x1409 lo
register map VX6854LC 48/114 docid027110 rev 2 4.24 fifo capability regi sters [0x1500 to 0x15ff] 4.25 csi lane mode capability register s [0x1600 to 0x1602] 0x140a hi matrix_element_blueingreen 16sr 00.00 ro color matrix parameter for blue in green 0x140b lo 0x140c hi matrix_element_redinblue 16sr 00.00 ro colo r matrix parameter for red in blue 0x140d lo 0x140e hi matrix_element_greeninblue 16sr 00.00 ro color matrix parameter for green in blue 0x140f lo 0x1410 hi matrix_element_blueinblue 16sr 01.00 ro color matrix parameter for blue in blue 0x1411 lo table 34. color matrix registers [0x1400 to 0x14ff] (continued) index byte register name data type default type comment table 35. fifo capability registers [0x1500 to 0x15ff] index byte register name data type default type comment 0x1500 hi fifo_size_pixels 16ui 07.00 ro VX6854LC has a fifo of 1792 pixels note: this value should be 1023 pixels 0x1501 lo table 36. csi llane mode capability registers [0x1600 to 0x1602] index byte register name data type default type comment 0x1600 ui_and_manual_dphy_ctrl_ca pability 8ui 03 ro csi2 dphy control capability bit0: automatic dphy control supported bit1:ui-based dphy control supported 0x1601 csi_lane_capability 8ui 01 ro one csi-2 data lane supported 0x1602 csi_signallingmode_capability 8ui 07 ro VX6854LC supports: bit0: ccp2 data/clock bit1: ccp2 data/strobe bit2: csi-2
docid027110 rev 2 49/114 VX6854LC register map 69 4.26 binning capability regi sters [0x1700 to 0x1719] 4.27 data transfer capability registers [0x1 800 to 0x1800] table 37. binning capability registers [0x1700 to 0x1719] index byte register name data type default type comment 0x1700 binning_capability 8ui 01 ro VX6854LC supports binning 0x1701 binning_sub_type 8ui 02 ro VX6854LC supports two binning types 0x1702 binning_type_1 8ui 22 ro binning type is 2x2 (col x row) 0x170b binning_weighting_capability 8ui 05 ro VX6854LC supports averaged and bayer corrected weighting 0x170c hi min_frame_length_lines_bin 16ui 00.19 ro minimum frame length allowed in binning mode. units: lines 0x170d lo 0x170e hi max_frame_length_lines_bin 16ui ff.ff ro maximum possible number of lines per frame allowed in binning mode. units: lines 0x170f lo 0x1710 hi min_line_length_pck_bin 16ui 09.c4 ro minimum line length allowed in binning mode. units: pixel clocks 0x1711 lo 0x1712 hi max_line_length_pck_bin 16ui 3f.ff ro maximum possible number of pixel clocks per line. allowed in binning mode units: pixel clocks 0x1713 lo 0x1714 hi min_line_blanking_pck_bin 16ui 05.a6 ro minimum line blanking time in pixel clocks allowed in binning mode units: pixel clocks 0x1715 lo 0x1716 hi fine_integration_time_min_bin 16ui 03.86 ro minimum fine integration time. pixel periods allowed in binning mode. value should be 0x0197 for 2x2 0x1717 lo 0x1718 hi fine_integration_time_max_ margin_bin 16ui 06.3e ro current line length ? current max fine exposure allowed in binning mode. pixel periods. value should be 0x080f for 2x2 0x1719 lo table 38. data transfer capability registers [0x1800 to 0x1800] index byte register name data type default type comment 0x1800 data_xfer_if_capability 8ui 0d ro VX6854LC supports interface 1 and requires polling for both read and write.
register map VX6854LC 50/114 docid027110 rev 2 4.28 shading correction capabilit y registers [0 x1900 to 0x1900] 4.29 defect correction capabilit y registers [0x1 903 to 0x1903] 4.30 edof capability regi sters [0x1980 to 0x19c0] table 39. shading correction capability registers [0x1900 to 0x1900] index byte register name data type default type comment 0x1900 shading_correction_capability 8ui 01 ro VX6854LC supports shading correction table 40. defect correction capability registers [0x1903 to 0x1903] index byte register name data type default type comment 0x1903 defect_correction_capability 8ui 0f ro VX6854LC supports the following defect correction: bit0: mapped couplet correction bit1: dynamic couplet correction bit2: single pixel defect correction bit3: single pixel defect correction weight adjustment table 41. edof capability registers [0x1980 to 0x19c0] index byte register name data type default type comment 0x1980 edof_capability 8ui 01 ro VX6854LC supports edof 0x1981 edof_estimation_frames 8ui 01 ro one estimation frame is required before edof is applied 0x1982 edof_supports_sharpness_adj 8ui 03 ro VX6854LC supports sharpness adjustment 0x1983 edof_supports_denoising_adj 8ui 03 ro VX6854LC supports denoising adjustment 0x1984 edof_supports_module_specif ic_adj 8ui 03 ro VX6854LC supports noise vs details adjustment 0x1985 edof_supports_depth_of_field _adj 8ui 00 ro VX6854LC does not support depth of field adjustment 0x1986 edof_supports_focus_distanc e_adj 8ui 03 ro VX6854LC supports focus distance adjustment 0x1988 edof_supports_ab_2x2 8ui 02 ro VX6854LC does not support binning 2x2 with edof 0x19c0 edof_estimation_mode_capab ility 8ui 0f ro edof supports following types: bit 0: uniform bit 1: centre weight bit2: large spot bit3: narrow spot
docid027110 rev 2 51/114 VX6854LC register map 69 4.31 color feedback capability registers [0x1987 to 0x1987] 4.32 manufacturer specific registers [0x3000 to 0x3fff] table 42. color feedback capab ility registers [ 0x1987 to 0x1987] index byte register name data type default type comment 0x1987 colour_feedback_capability 8ui 02 ro VX6854LC requires awb gain feedback table 43. manufacturer specific registers [0x3000 to 0x3fff] index byte register name data type default type comment 0x3050 dark_setup 8b 05 rw bit_0: 0 : do not apply any offset. 1 : apply an offset. 0x3516 hi pll_mod_period 16ui 00.00 rw sscg config input to set modulation period and depth (13bit) 0x3517 lo 0x3518 hi pll_inc_step 16ui 00.00 rw sscg config input to set modulation depth (15bit) 0x3519 lo 0x5024 sscg_static_ctrl 8b 00 rw (1) bit0: 0 - sscg deactivated 1 - sscg activated bit1: 0 - sscg - center spread 1 - sscg - down spread 1. in order to read this register, the non-smia address range must be enabled by writing 0x3640=0.
video data interface VX6854LC 52/114 docid027110 rev 2 5 video data interface the video stream which is output from the VX6854LC using the compact camera port (ccp) or camera serial interface (csi) contains bo th video data and other auxiliary information. this chapter describes the frame formats. the VX6854LC is smia version 1.0 and mi pi csi-2 version 1.00 and d-phy 0.90 compliant. the selection of the video data format is controlled using the following register: csi_signalling_mode (0x0111) 0 - ccp2 data/clock 1 - ccp2 data/strobe 2 - csi-2 (default) changing the video data format must be performe d when the sensor is in software standby. ? the VX6854LC has one csi-2 data lane capable of transmitting at 800 mbps. ? the csi-2 data lane transmitter supports: ? unidirectional master ?hs-tx ? lp-tx (ulps) ? cil-muyn function ? the csi-2 clock lane transmitter supports: ? unidirectional master ?hs-tx ? lp-tx (ulps) ? cil-mcnn function 5.1 frame format the frame format for the VX6854LC is described by the frame format description registers, see table 13 on page 31 . for ccp this results in a frame as shown in figure 12 and for csi it results in a frame as shown in figure 13.
docid027110 rev 2 53/114 VX6854LC video data interface 69 figure 12. VX6854LC ccp frame format figure 13. VX6854LC csi-2 frame format embedded data lines the embedded data lines provide a mechanism to embed non-image data such as sensor configuration details and image statistics values with a frame of data. VX6854LC has two embedded data lines at the start of the frame. dummy columns the VX6854LC has 0 dummy columns. visible pixel data the visible pixels contain valid image data.the correct integration time and analogue gain for the visible pixels is specified in the emb edded data lines at the start of the frame. the number of visible pixels can be varied. interline padding interframe padding bayer pixel data ccp embedded line start codes ccp embedded checksum codes ccp embedded line end codes fe fs embedded data lines frame start code frame end code dummy columns bayer pixel data fs fe em bedded data packet header, ph packet footer, pf line b lanking fram e blanking fram e end p acket fram e s tart p acket
video data interface VX6854LC 54/114 docid027110 rev 2 black pixel data (zero integration time) the VX6854LC has 0 black pixels. dark pixel data (light shielded pixels) the VX6854LC has 0 dark pixels. manufacturer specific pixel data the VX6854LC has 0 manufacturer specific pixels. interline padding/line blanking during interline padding all bits in the data stream in a ccp frame are set to 1. in a csi-2 frame there is no concept of line blanking being transmitted, the sensor will simply spend a longer time in the lp state between active line data. interframe padding / frame blanking during interframe padding all bits in the data stream in a ccp frame are set to 1. in a csi-2 frame there is no concept of fram e blanking being transmitt ed, the sensor will simply spend a longer time in the lp state at the end of the active data for a frame.
docid027110 rev 2 55/114 VX6854LC video timing 69 6 video timing 6.1 output size the VX6854LC has the following methods availa ble to achieve the required output size, these can be used independently or in conjunction with any other: ? programmable addressable region of the pixel array ? programmable width and height for output image data ? scaling ? subsampling the programmable image size and output si ze are independent functions. it is the responsibility of the ho st to ensure that these function s are programmed correctly for the intended application. these functions also redu ce the amount of data and therefore reduce the peak data rate of ccp2/csi-2. 6.1.1 programmable addressable region of the pixel array the native size for the VX6854LC is 2048 x 1536, the maximum addressable array is 2064 x 1552 which gives border (outer 8 rows and 8 columns) pixels for the color reconstruction algorithms to use at the edges of the array. by programming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers it is possible to use the full size of the array as yo u would do for a native size output or you can select a ?window of interest?. the addressed re gion of the array is used in any subsequent sub-sampling or scaling. figure 14. programmable addressable region of the pixel array y_addr_max =1551 x_addr_max =2063 y_addr_min = 0 x_addr_min = 0 x_addr_max, y_addr_max x_addr_end, y_addr_end addressed pixel array region x_addr_start, y_addr_start x_addr_min, y_addr_min
video timing VX6854LC 56/114 docid027110 rev 2 the host must ensure the following rules are kept: ? the end address must be greater than the start address ? the x and y start addresses are restricted to even numbers only, and the x and y end addresses are restricted to odd numbers only, to ensure that there is always a even number of pixels readout 6.1.2 programmable width and he ight for output image data the x_output_size and y_output_size registers are not intended as the primary cropping controls. they are intended to define the position of th e le/fe codes in the ccp data frame so that the sensor does not need to calculate this based on region of interest or sub-sampling settings. it should be expected that the host w ill set the output sizes to exactly enclose the output image data. if the host should not do th is, the VX6854LC will treat the output sizes as being calculated from the top left hand corner of the output array. so in the case where output sizes are smaller than the output data, the data shall be cropped from its right hand and lower limits. in the case where larger than the output data, the lines shall be padded out to the defined output size with undefined data. figure 15. output size within a ccp data frame note: ccp2 requires that the number of pixels between the line start and line end sync codes for: ? raw8 is a multiple of 4 pixels ? raw10 is a multiple of 16 pixels the host must control the x_output_size to ensure that the above criteria is met. 6.1.3 scaling the VX6854LC module is compliant with the ?prof ile level 2 - full (horizontal & vertical)? level of image scaling. the image scaling function within the sensor module provides a flexible way of generating lower resolution full field of view image data, at a reduced data rates, for viewfinder and video applications. ccp output active line length interline padding interframe padding x_output_size y_output_size output data ccp embedded line start codes ccp embedded checksum codes ccp embedded line end codes fe fs embedded data lines dummy columns
docid027110 rev 2 57/114 VX6854LC video timing 69 the scaler is able to scale the full resolution of the sensor module down to within 10% of a the target image size (the smallest output size is 256x192). this fl exibility means that the VX6854LC module can support a wide range of lcd viewfinder sizes and different codec resolutions. the VX6854LC has three scaling modes which are controlled by the scaling_mode register as shown in figure 16 . figure 16. scaling modes scaler quality the scaler supports two options for the spatial sampling of the scaled image data (see figure 17 ): ? bayer sampled scaled image data the sampling point for the scaler for the output gr value appears to be in the centre of the gr pixel (that is, between the first an d second pixels and between the first and second rows of the original input bayer pixel data). the r (or b) sampling points are similarly in the centre of the r pixel (or b pixel). ? co-sited scaled image data the sampling point for the gr, r. gb and b vales in each output ?quad? are functions of the same colour input array pixels such that the spatial sampling point for all four appears to be in the centre of the ?quad?, that is, between the second and third pixels and between the first and second rows. the spatial sampling mode is controlled by the spatial_sampling register. pixel array output scaling_mode register VX6854LC output 0- no scaling 1- horizontal scaling 2- full scaling (horizontal and vertical)
video timing VX6854LC 58/114 docid027110 rev 2 figure 17. scaler quality down scaler factor the down scaler factor is controlled by an m/n ratio, scale_m is >= 16 and scale_n is fixed at 16. scale_m is in the range 16 to 129. this single down scale factor is used by both the horizontal and vertical scalers. the scaler acts upon the addressed region of the array which is determined by the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. if the down scale factor is greater than 1.0, then the derating factor must also be set greater than 1.0. refer to section 6.2.4: derating on page 63 for details. note: the derating can be set to a minimum value, for example if op_pix_clk_div=10, setting vt_pix_clk_div=9 would meet this requirement. figure 18. example image full scaled by a downscale factor of 2 pixel array output bayer sampled scaling co-sited sampling down_scale_factor = scale_m scale_m scale_n 16 = downscale by 2 full (horizontal and vertical) scaling raw bayer image
docid027110 rev 2 59/114 VX6854LC video timing 69 6.1.4 subsampling subsampling is achieved by programming the x _odd_inc, y_odd_inc, x_even_inc and y_even_inc registers. if the pixel being readout has an even address then the address is incremented by the even increment value either x_even_inc or y_even_inc. if the pixel being readout has an odd address then the address is incremented by the odd increment value either x _odd_inc or y_odd_inc. the sub_sampled readout is disabled by setting the odd and even increment values to 1. sub-sampling acts upon the addressed region of the array which is determined by the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. for the edof focus estimation to operate ef fectively, the x_even_inc and y_even_inc registers must be 1. the equation for the sub-sampling factor is given below: figure 19. sub-sample readout example sub_sampling_factor even_inc odd_inc + 2 -------------------------------------------------- - = 8 5 6 7 g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b g gr r b 4 1 2 3 9 10 8 567 4 123 9 010 0 111 33 3 1 1 1 3 3 3 example: x_even_inc=1 control range: min_even_inc=1 min_odd_inc=1 max_even_inc=7 max_odd_inc=7 x_odd_inc=3 y_even_inc=1 y_odd_inc=3
video timing VX6854LC 60/114 docid027110 rev 2 6.1.5 binning the VX6854LC also has a binning mode, that offe rs a reduced size full field of view image. the binning mode averages row and column pixel data. the binning mode results in a reduced number of lines and so can be used to give a higher image frame rate. compared to sub-sampling, binning makes use of the light gathered from the whole pixel array and it re sults in higher image quality. the binning mode will scale by 2x2 in the x and y direction. for cut 1 silicon, entering and exiting binning mode must be performed when the sensor is in software standby. (this is not a requirement for cut 2.x silicon). table 44 summarizes the register settings for ea ch of the binning mo des. refer to the personality file for additio nal settings to optimise the image quality performance. binning repair binning can introduce some phases errors from the image perspective as it clusters the output of each color channel. gr, r, b and gb binned pixels are located around the same intersection point on the output lattice. to reduce this error, a binning ip is integrated into the imaging data path. the ip moves each binned color channel by 1/8th of an inter-pixel distance. therefore the top-left gr pixel moves into the top-left corner, the r pixel in the top-right moves in the top-right direction. this is shown in figure 20 . figure 20. binning repair table 44. binning register settings register address normal 2x2 binning_mode 0x0900 0x00 0x01 binning_type 0x0901 n/a 0x22 binning_weighting 0x0902 n/a 0x04 x_odd_inc 0x0383 0x01 0x03 y_odd_inc 0x0387 0x01 0x03
docid027110 rev 2 61/114 VX6854LC video timing 69 6.2 video timing this section specifies the timing for the image data that is readout from the pixel array and the output image data. these are not necessarily the same size. the application of all of the video timing read/w rite parameters must be re-timed to the start of frame boundary to ensure that the parameters are consistent within a frame. the video stream which is output from the VX6854LC contains both video data and other auxiliary information. the vx685 4lc output coding conforms to the ccp raw8 and raw10 data format (see smia 1.0 part 2:ccp2 specification) including line checksums. reference smia 1.0 specification section 5 for detailed description of video timing. 6.2.1 pll block the VX6854LC contains a pll (phase locked loop) block, which generates all the necessary internal clo cks from the external clock input. ch anges to the pll settings on the VX6854LC will only be consumed on the software standby to streaming mode transition. figure 21 shows the internal functional blocks, which define the relationship between the external input clock frequency and the pixel clock frequency. the majority of the logic withi n the device is clocked by vt_sys_clk however the cci block is clocked by the external input clock. figure 21. VX6854LC clock relationships min. 37 max. 134 pll_multiplier pre_pll_ clk_div range 1, 2, 4 ext. input clock external input clock ext_clk_freq_mhz pll input clock pll_ip_clk_freq_mhz pll output clock pll_op_clk_freq_mhz video timing pixel clock vt_pix_clk_freq_mhz video timing system clock vt_sys_clk_freq_mhz range 1, 2 vt_sys_clk _div vt_pix_clk _div min. 4 max. 10 output timing system clock op_sys_clk_freq_mhz output timing pixel clock op_pix_clk_freq_mhz op_pixel _clk_div op_sys_ clk_div min. 1 max. 66 range 8, 10 max 27mhz 6mhz min min min min min min min max max max max max max 800mhz 80mhz 38mhz 122mhz 0.757mhz 80mhz 800mhz 7.57mhz (1) 450mhz 800mhz 6mhz 12mhz 1. note that the minimum op_sys_clk_freq_mhz is 80mhz in csi2 mode.
video timing VX6854LC 62/114 docid027110 rev 2 the equation relating the input clock frequency to pixel clock frequencies are given below: 6.2.2 spread spectrum clock generator the pll contains a spread spectrum clock generator block (sscg) for the purposes of emi reduction. this feature is off by default and is intended for use if channel blocking becomes an issue on the baseband platform. a primary source of emi is the high speed ccp serial data link. the modulation period and depth are fully programmable. the spread mode is selectable between center spread (default) or down spread. the sscg registers can only be reprogrammed with new values when the sensor is in software standby mode. 6.2.3 framerate the framerate of the array readout and theref ore the output framerate is governed by the line length, frame length and the video timing pixel clock frequency. ? line length is specified as a number of pixel clocks, line_length_pck. ? frame length is specified as a numb er of lines, frame_length_lines. ? video timing pixel clock is specif ied in mhz, vt_pix_clk_freq_mhz. the equation relating the framerate to the line length, frame length and the video timing pixel clock frequency is given below: table 45 provides examples of frame timing for raw10 mode for 20 fps for a variety of external clock frequencies. table 46 provides examples of frame timing for raw10 mode for 15 fps for a variety of external clock frequencies. vt_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier pre_pll_clk_div vt_sys_ clk_div vt_pix_clk_div ------------------------------------------------------------------------------------------------------------------------------- - = op_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier pre_pll_clk_div op_sys_cl k_div op_pix_clk_div ------------------------------------------------------------------------------------------------------------------------------- ------ = table 45. external clock frequency exampl es, 3.15 mpixel raw1 0 20 fps (csi-2 only) ext clk freq pre-pll clk div pll multiplier vt sys clk div vt pixel clk div video timing pixel clock line length frame length mhz integer integer (dec) integer integer mhz pixel clks s lines (dec) 9.60 1 83 1 10 79.680 2500 31.37 1594 12.00 2 133 1 10 79.800 2500 31.32 1596 13.00 2 123 1 10 79.950 2500 31.27 1599 framerate vt_pix_clk_freq_mhz line_length_pck frame_length_lines -------------------------------------------------------------------------------------------------- =
docid027110 rev 2 63/114 VX6854LC video timing 69 note: op_sys_clk_div should eq ual vt_sys_clk_div and op_pix_clk_div should equal vt_pix_clk_div for these examples. 6.2.4 derating to provide a wide range of data rate reduction options the full image scaler is able to reduce the data and therefore data rates in both t he horizontal and vertical directions. in the VX6854LC this is achieved by the use of a fifo between video timing and output clock domains. it is therefore necessary for the host to confi gure the op clock domain to ensure that the fifo neither over flows or under flows figure 22. timing block diagram table 46. external clock frequency examples, 3.15 mpixel raw10 15 fps (csi-2 or ccp) ext clk freq pre-pll clk div pll multi- plier vt sys clk div vt pixel clk div video timing pixel clock line length frame length mhz integer integer (dec) integer integer mhz pixel clks s lines (dec) 9.60 1 66 1 10 63.360 2500 39.46 1690 12.00 2 106 1 10 63.600 2500 39.31 1696 13.00 2 98 1 10 63.700 2500 39.25 1699 pre pll pll vt sys vt pixel op sys op pixel pixel array scaler fifo tx logic output clock domain video timing clock domain
video timing VX6854LC 64/114 docid027110 rev 2 derating shows the difference between the video timing domain and the output clock domain. fifo the fifo is used to implement the data rate reduction required for profile 1 and 2 operation. the concept of an output frame length and a line length for the output timing domain does not exist for smia devices such as the VX6854LC. this is a result of the fifo input data patterns being different depending on scaling factor and if the data is co-sited or bayer sampled, which results in vari able interframe and interline blanking time between lines and between frames. figure 23. smia output timing when the fifo reaches a certain level of usage the ccp transmitter starts outputting a line containing x_output_size pixels . this then naturally tracks any variation in the input data rate, if the water mark is set co rrectly underflow is not possible. figure 24. fifo water mark control if the derating factor >= downscale factor then the average input rate of a burst of a line of scaler output data into the fifo is always faster than the output data rate, in this case the derating = vt_sys_clk_div * op_pix_clk_div op_sys_clk_div * vt_pix_clk_div output data: ccp active video 2064 pixels by 1552 lines line blanking output frame length does not exist in smia output line length does not exist in smia cs le fifo water mark level = ccp output trigger fifo usage ls ls le cs data data x_output_size + additional_cols x_output_size + additional_cols
docid027110 rev 2 65/114 VX6854LC video timing 69 fifo_water_mark_pixels can be set to 40 as the fi fo input data rate is always faster than the fifo output data rate. if the derating factor < downscale factor then the average input rate of a burst of a line of scaler output data into the fifo is slower than the output data rate, in this case the fifo_water_mark_pixels must be set to avoid underflow. calculate the floating point value of the fifo_water_mark_pixels then round up this value; * scale_factor scale_factor - derating x_output_size fifo_water_mark_pixels(flt)= fifo_water_mark_pixels = fif o_water_mark_pixels(flt) + 40
video timing VX6854LC 66/114 docid027110 rev 2 6.3 bayer pattern the three color (red, green, blue) filters are ar ranged over the pixel array in a repeated 2x2 arrangement known as the bayer pattern. when the sensor array is read, the output order of red, green, blue depends on the settings of vertical flip and horizontal mirror. see figure 25 for read-out order for the default settings of vertical flip and horizontal mirror both turned off. vertical flip will change the fi rst line to be output from a green/red line to a blue/green line and horizontal mirror will change the sequence wit hin a line, sa y, green/red to red/green. as shown in figure 25 , the first pixel to be readout fr om the imaging array will be green followed by red. figure 25. bayer pattern blue green green red blue green green red 3 2 1 0 1 3 2 0 5 4 blue green green red 5 4 7 6 2059 2058 2057 2056 1548 1550 1549 1547 2061 2060 1552 1551 2063 2062 blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red 1552 active rows
docid027110 rev 2 67/114 VX6854LC video timing 69 6.4 image compression the objective of the image compression is to reduce the required bandwidth in transmission between the sensor and the host. the key features of the dpcm/pcm compression algorithm are: ? visually lossless ? low cost implementation (no line memories are required) ? fixed rate compression the 10-bit to 8-bit dpcm/pcm image compression algorithm is supported by VX6854LC. 10-bit to 8-bit compression has the additional advantage that one pixel value equals 1 byte of data. the level of compression is controlled via the csi_data_format register. the same register is also used to enable and disable compression. the compression_mode register is used to select which compression algorithm is used. currently only the dpcm/pcm tech nique is supported. therefore th e value of this register is always 0x01. the compression_capability regist er tells the host whether a s ensor module does or does not have compression and if it has compress ion then what is the compression technique. again currently only the dpcm /pcm technique is supported. please also refer to section 10 of the smia1.0 specif ication document. 6.5 exposure and gain control VX6854LC does not contain any form of automatic exposure control. to produce a correctly exposed image the integration period and analogue gain for the pixels must be calculated by an exposure control algorithm implemented externally. the parameters are written to the VX6854LC using the cci interface. the exposure control parameters available on VX6854LC are: ? fine integration time ? coarse integration time ? analogue gain ? digital gain the exposure control parameter registers are defined in chapter 4: register map on page 29 . integration time and analogue gain capability registers should be used to determine the exposure control parameter limits for a given video timing configuration. see section 6.7 of the smia 1.0 part 1 specification for more info rmation on how to interpret the integration and gain capability registers and how to calculate exposure and gain limits. 6.5.1 analogue gain model VX6854LC only supports the single global analogue gain mode. VX6854LC has a 16-bit register (0x0204 and 0x0205) to control analogue gain. however, only 4 bits are supported by the smia1.0 description. two extra bits ca n be used for fine gain between values 8 and 16 but their description is not currentl y supported by smia1.0 specification.
video timing VX6854LC 68/114 docid027110 rev 2 figure 26 shows the way the analogue gain bits are used for VX6854LC. use only coarse gain bits for standard 1/x functionality . figure 26. analogue gain register format the following generic equation describes VX6854LC coarse gain behavior specified by the analogue gain description registers 0x008a to 0x0093: where: ? m1 = -1 ? c0 = 256 ? c1 = 256 table 47 specifies the valid analogue gain values for VX6854LC. also refer to section 6.3 of the smia1.0 specification document. table 47. analogue gain control gain value (0x0204/0x0205) coarse gain code [a7:a4] coarse analogue gain fine gain code [a3:a2] fine analogue gain 0x0000 0000 0.0 db (x1.00) 00 n/a 0x0010 0001 0.6 db (x 1.07) 00 n/a 0x0020 0010 1.2 db (x1.1) 00 n/a 0x0030 0011 1.8 db (x1.2) 00 n/a 0x0040 0100 2.5 db (x1.3) 00 n/a 0x0050 0101 3.3 db (x1.5) 00 n/a 0x0060 0110 4.1 db (x1.6) 00 n/a 0x0070 0111 5.0 db (x1.8) 00 n/a 0x0080 1000 6.0 db(x2.0) 00 n/a 0x0090 1001 7.2 db (x2.3) 00 n/a 0x00a0 1010 8.5 db (x2.7) 00 n/a 0x00b0 1011 10.1 db (x3.2) 00 n/a 0x00c0 1100 12.0 db (x4.0) 00 n/a 0x00d0 1101 14.5 db (x5.3) 00 n/a 0x00e0 1110 18.1 db (x8.0) 00 n/a 0x00e4 1110 fine ctrl 01 19.2 db (x9.1) 0x00e8 1110 fine ctrl 10 20.6 db (x10.7) 0x00ec 1110 fine ctrl 11 22.1 db (x12.8) 0x00f0 1111 24.1 db (x16.0) 00 n/a a7 a6 a5 a4 a3 a1 a0 a8 a9 a15 a14 a13 a12 a11 a10 a2 coarse gain fine gain not used not used gain c0 m ( 1x ? ? c1 ) + =
docid027110 rev 2 69/114 VX6854LC video timing 69 6.5.2 digital gain to help compensate for the relatively coarse analogue gain steps, VX6854LC contains a digital multiplier to ?fill? in the missing step s. by mixing analogue and digital gain it is possible to implement 3% gain steps across the full 1x to 16x gain range the details of the digital gain implementation are: ? four individual 16-bit digital channel gains (one per bayer channel) ? digital_gain_greenr (0x020e and 0x020f) ? digital_gain_red (0x0210 and 0x0211) ? digital_gain_blue (0x0212 and 0x0213) ? digital_gain_greenb (0x0214 and 0x0215) ? the digital gain range for each channel is 1.000 to 1.96875 in steps of 0.03125 (1/32), that is, 5 fractional bits ? digital_gain_min {0x1084:0x1085} = 0x0100 (1.00) ? digital_gain_max {0x1086:0x1087} = 0x01f8 (1.96875) ? digital_gain_step {0x1088:0x1089} = 0x0008 (0.03125) 6.5.3 integration and gain parameter re-timing the modification of exposure parameter (coarse, fine, clock division or gain) register values does not take effect immediately. the exact time at which changes to certain pa rameters take effect is controlled both to ensure that each frame of image data produced has consistent settings and that changes in groups of related parameters are synchronized. to eliminate the possibility of the sensor arra y seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to the serial interface register map. thus if the 5 bytes of exposure and gain data is sent as an auto- increment cci sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. however if it is not possible for the host to use auto-increment cci register accesses and only discrete register accesses are possible then the VX6854LC has a mechanism to temporarily suspend the automatic applicatio n of updated exposure register values. a group of parameter changes is marked by the host using a dedicated boolean control parameter, grouped_parameter_hold (register 0x0104). any changes made to ?retimed? parameters while the groupe d_parameter_hold si gnal is in the ?hold? state will be considered part of the same group. only when the grouped_parameter_hold control signal is moved back to the default ?no-hold? state should the group of changes be executed.
electrical characteristics VX6854LC 70/114 docid027110 rev 2 7 electrical characteristics refer to smia characterization specificat ion - revision 1, smia ccp2 specification ecr0002 - revision 1 and smia ccp2 specification - revision 1 (see table 3: reference documents on page 14 ). typical values quoted for nominal voltage, process and temperature. maximum values are quoted for wo rst case conditions (process, voltage and functional temperature) unless otherwise specified. 7.1 operating conditions table 48. operating conditions symbol parameter min. typ. max. unit voltage vdig digital power supply 1.68 1.8 1.92 v vana analog power supply 2.3 2.8 2.9 v vip(dig) digital input voltage (1) 1. digital input: extclk, xshutdown, scl, sda 0 - 1.92 v temperature t as temperature (storage (2) ) 2. camera has no permanent degradation. -40 - +85 c t af temperature (functional operating (3) ) 3. camera is electrically functional. -30 +70 c t an temperature (normal operating (4) ) 4. camera produces ?acceptable? images. -25 +55 c t ao temperature (optimal operating (5) ) 5. camera produces optimal optical performance. +5 +40 c t at temperature (test (6) ) 6. 100% tested parameters are measured at this temperature. +21 +25 c
docid027110 rev 2 71/114 VX6854LC electrical characteristics 80 7.2 absolute maximum ratings caution: stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating on ly and functional operati on of the device at these or any other conditions above those in dicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.3 power supply 7.3.1 power supply - vdig, vana table 49. absolute maximum ratings symbol parameter min. max. unit v digmax digital power supply -0.3 2.2 v v anamax analog power supply -0.3 3.2 v v ihmax extclk, xshutdown, scl, sda -0.3 vdig + 0.5 v v cap vcap analogue voltage -0.3 4.2 v t sto storage temperature -40 + 85 (1) 1. this is a maximum long term standard storage temper ature, see soldering profile for short term high temperature tolerance. o c v esd electrostatic discharge model human body model (2) charge device model (3) 2. hbm tests are performed in compliance with jesd22-a114f 3. cdm tests are performed in compliance with jesd22-c101d -2.0 -500 2.0 500 kv v table 50. power supplies vdig, vana parameter digital analogue unit typ. max. typ. max. hardware standby 10 30 10 40 a software standby: ext. clock not switching ext. clock = 9.6mhz (1) 1. the digital current scales linearly with the external clock frequency used. 7 10 20 25 0.6 0.6 1.0 1.0 ma ma streaming: preview (2) capture still (3) 2. profile 0, 30fps, 10-10 data, csi-2, binning 2x2 image, edof estimation mode 3. profile 0, 15fps, 10-10 data, csi-2, full resolution image, edof application mode 60 65 85 95 40 40 65 65 ma ma
electrical characteristics VX6854LC 72/114 docid027110 rev 2 7.3.2 power supply (peak current) - vdig, vana the peak current (in-rush) consumption of th e sensor module is defined as any current pulse >=10 s. the duty cycle of the peak to the low part of the current profile is 33% with a worst-case period of 500 s. for table 51. in-rush current vd ig, vana for ccp2 interface parameter digital analog unit typical maximum typical maximum boot clock peak current (1) 1. this corresponds to the transient current when xshutdown is powered up and the sensor is being set sw_standby mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 70 100 190 200 ma start streaming current (2) 2. when the sensor is changed from software standby to streaming mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 60 85 190 200 ma stop streaming current (3) 3. when the sensor is changed from streaming to soft ware standby. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 150 160 80 90 ma in streaming mode while changing sensor settings 150 190 90 90 ma table 52. in-rush current vd ig, vana for csi-2 interface parameter digital analog unit typical maximum typical maximum boot clock peak current (1) 1. this corresponds to the transient current when xshutdown is powered up and the sensor is being set sw_standby mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 110 135 210 220 ma start streaming current (2) 2. when the sensor is changed from software standby to streaming mode. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 150 230 135 160 ma stop streaming current (3) 3. when the sensor is changed from streaming to soft ware standby. max value is given for max vdd and 70c temperature. typical value is for 25c and vdd is set to nominal value. 160 190 140 140 ma in streaming mode while changing sensor settings 190 230 140 140 ma
docid027110 rev 2 73/114 VX6854LC electrical characteristics 80 7.3.3 power supply ripple requirement it is recommended that the application meets the following requirements on the power supply signal in 10 khz to 1.4 mhz. 7.4 system clock - extclk 7.5 power down control - xshutdown table 53. ripple requirement symbol parameter max. unit ripple_vana peak to peak max ripple on analogue power supply ( 10 khz to 1.4 mhz ) 6mv ripple_vdig peak to peak max ripple on digital power supply 50 mv table 54. system clock - extclk symbol parameter min. max. unit leakage current 4 (1) 1. with dc coupled square wave clock. 30 (2) 2. with dc vdig applied. a v cl dc coupled square wave low level 0 0.3 * vdig v v ch dc coupled square wave high level 0.7 vdig vdig+0.5v v v cac ac coupled sine wave 0.5 1.2 v f extclk clock frequency input 6.0 - 1% (3) 3. nominal frequencies are 6.0 to 27 mhz with a 1% c entre frequency tolerance. tested at characterization only. 27 + 1% (3) mhz duty cycles clock frequency duty cycles 40 60 % input jitter extclk input jitter - refer to jitter application note (4) 4. stmicroelectronics will prov ide upon request an application note detailing the extclk input jitter requirements. ps table 55. power down control - xshutdown symbol parameter min. typ. max. unit v il low level input voltage 0 - 0.3 * vdig v v ih high level input voltage 0.7 * vdig - vana v i l input leakage current (1) 1. with vgnd v xshutdown vdig -15 15 a
electrical characteristics VX6854LC 74/114 docid027110 rev 2 7.6 cci interface - sda, scl 7.6.1 cci interface - dc specifications 7.6.2 cci interface - timing characteristics table 56. cci interface symbol parameter min. max. unit v il low level input voltage 0 0.3 * vdig v v ih high level input voltage (vdig > 1.7v) 0.7 * vdig vdig+0.5v v high level input voltage (vdig < 1.3v) 0.77 vdig+0.5v v v ol low level output voltage (1) 1. v oh not valid for cci. 3 ma drive strength 0 0.2 * vdig v i il low level input leakage - -15 a i ih high level input leakage - 15 a table 57. cci interface - timing characteristics symbol parameter min. typ. max. unit t scl scl clock frequency 0 - 400 khz t low clock pulse width low 1.3 - - s t high clock pulse width high 0.6 - - s t sp pulse width of spikes which are suppressed by the input filter 0 - 50 ns t buf bus free time between transmissions 1.3 - - s t hd.sta start hold time 0.6 - - s t su.sta start set-up time 0.6 - - s t hd.dat data in hold time 0 - 0.9 s t su.dat data in set-up time 100 - - ns t r scl/sda rise time 20+0.1 cb (1) 1. cb = total capacitance of one bus line in pf - 300 ns t f scl/sda fall time 20+0.1 cb (1) - 300 ns t su.sto stop set-up time 0.6 - - s ci/o input / output capacitance (sda) - - 8 pf cin input capacitance (scl) - - 6 pf
docid027110 rev 2 75/114 VX6854LC electrical characteristics 80 figure 27. cci ac characteristics all timings are measured from either 0.3 vdig or 0.7 vdig. for further information on the cci interface please refer to the specif ication document: smia 1.0 part 2: ccp specification. 7.7 ccp interface 7.7.1 ccp interface - dc specifications note: for further information on the sublvds refer to the following specification document: smia 1.0 part 2: ccp2 specification sda scl t hd.sta t r t high t f t su.dat t hd.dat t su.sta t su.sto ... ... t hd.sta t low t buf stop start stop start 0.7 vdig 0.3 vdig 0.3 vdig 0.7 vdig table 58. ccp interface - dc specifications symbol parameter min. typ. max. unit v od differential voltage swing (1) 1. measured over a 100 load 100 150 200 mv v cm common mode voltage (self biasing) 0.8 0.9 1.0 v r o output impedance 40 140 i dr drive current range (internally set by bias circuit) 0.5 1.5 2 ma psrr (2) 2. nominal value for the interference at v cm voltage through digital supply relative to the interference at digital supply over the 0-1 ghz operat ing range. psrr = 20*log10 (v dig interference (peak-to-peak) / v cm interference (peak-to-peak)) 0 - 100mhz - - 30 db 100 - 1000mhz - - 10 db
electrical characteristics VX6854LC 76/114 docid027110 rev 2 7.7.2 ccp interface - timing characteristics the parameters in table 59 are measured across a terminated 100 transmission line. ccp2_signalling_mode register is set to 1, data/strobe mode. figure 28. sublvds ac timing for further information on the ccp refer to th e specification document: smia 1.0 part 2: ccp2 specification 30-6-04. table 59. ccp interface - timing characteristics symbol parameter min. max. unit f p average data frequency - 640 mbits/s t p average data period 1.56 - ns t jitter (1) 1. t pmax -t pmin data period jitter - 200 ps t stable both data and clock at the stable level 780 - ps t rise rise time of data+/data- ,clk+/clk- 300 400 ps t fall fall time of data+/data-, clk+/clk- 300 400 ps t shew (2) 2. t shew =t cmpshew + t chcshew total skew between signals - 225 ps t pwr power up/down time - 20 s data+/ data- clk+/ clk- t cmpshew t stable t chcshew t pmin t pmax t fall t rise 80% 0.9v 20% 80% 0.9v 20%
docid027110 rev 2 77/114 VX6854LC electrical characteristics 80 7.8 csi-2 interface 7.8.1 csi-2 interface - dc specifications note: when quoting the mipi specificatio n, the following rules must be followed: disclosure of a specification, or the creation of derivative works of a specification, may also be made ?as part of stmicroe lectronics?s product for the purpo se of developing and selling products complying with the mipi specification(s).? ma 3.2(c). in this connection, the mipi board has approved the disclosure only of su ch portion of the specification as in the reasonable judgment of the member is rele vant for the development and/or sale of compliant portions. this may, of course, require the disclosure of the entire specification when the situation requires. the board notes th at these provisions of the ma are intended to assist members in providing information usef ul in mipi compliant product development or to provide support documentation for the member's products. disclosure is also permitted when, in the opinio n of the mipi board, such disclosure is a legitimate derivative use which enables the development or implementation of a mipi specification or development or sale of compliant portions. pe rmission for such disclosures may be granted by the mipi board on a case by case basis and subject to the receipt of a confidentiality agreement as in the case of a contractor. examples of such a derivative use may be disclosures to vendors of test equipment or other enabling products. note: in all permitted cases of disclosure of a mipi specific ation, in whole, or in part, the disclosure must include (a) the copyright notice contain ed in the specification on the first page of the disclosed portion and on every other page where it appears in the included portions of the specification with prominence at least equal to that of the specification as published by mipi. the copyright notice on the first page shall be followed by the following language: ?all rights reserved. this material is reprinted with the permission of the mipi alliance, inc. no part(s) of this document may be disclosed, r eproduced or used for any purpose other than as needed to support the use of t he products of stmicroelectronics?. table 60. csi-2 interface - high speed mode - dc specifications symbol parameter min. typ. max. unit v cmtx hs transmit static common mode voltage 150 200 250 mv v od hs transmit differential voltage (1) 1. value when driving into load impedance anywhere in the z id range (80-125 ). 140 200 270 mv v ohhs hs output high voltage (1) 360 mv z os single ended output impedance 40 50 62.5 table 61. csi-2 interface - low power mode - dc specifications symbol parameter min. typ. max. unit v oh output high level 1.1 1.2 1.3 v v ol output low level -50 50 mv z olp output impedance of lp transmitter 110
electrical characteristics VX6854LC 78/114 docid027110 rev 2 7.8.2 csi-2 interface - ac specifications for further information on the sublvds refer to the spec ification document: mipi alliance standard for d_phy version 0.90. note: when quoting the mipi specificatio n, the following rules must be followed: disclosure of a specification, or the creation of derivative works of a specification, may also be made ?as part of stmicroe lectronics?s product for the purpo se of developing and selling products complying with the mipi specification(s).? ma 3.2(c). in this connection, the mipi board has approved the disclosure only of su ch portion of the specification as in the reasonable judgment of the member is rele vant for the development and/or sale of compliant portions. this may, of course, require the disclosure of the entire specification when the situation requires. the board notes th at these provisions of the ma are intended to assist members in providing information usef ul in mipi compliant product development or to provide support documentation for the member's products. disclosure is also permitted when, in the opinio n of the mipi board, such disclosure is a legitimate derivative use which enables the development or implementation of a mipi specification or development or sale of complia nt portions. permission for such disclosures may be granted by the mipi board on a case by case basis and subject to the receipt of a confidentiality agreement as in the case of a contractor. examples of such a derived use may be disclosures to vendors of test equipment or other enabling products. note: in all permitted cases of disclosure of a mipi specific ation, in whole, or in part, the disclosure must include (a) the copyright notice contain ed in the specification on the first page of the disclosed portion and on every other page where it appears in the included portions of the specification with prominence at least equal to that of the specification as published by mipi. the copyright notice on the first page shall be followed by the following language: ?all rights reserved. this material is reprinted with the permission of the mipi alliance, inc. no part(s) of this document may be disclosed, r eproduced or used for any purpose other than as needed to support the use of t he products of stmicroelectronics?. table 62. csi-2 interface - high speed mode - ac specifications symbol parameter min. typ. max. unit data rate 80 - 800 mbits/s t clkp average data period 1.25 - ns t r and t f 20% - 80% rise time and fall time 150 0.3ui (1) 1. ui is equal to 1/(2*fh) where fh is the fundamental frequency of the transmission for a certain bit rate. e.g. for 600mbps fh is 300mhz. ps t skew data to clock skew -0.15ui - 0.15ui ps table 63. csi-2 interface - low power mode - ac specifications symbol parameter min. typ. max. unit t r and t f 15% - 85% rise time and fall time 25 ns
docid027110 rev 2 79/114 VX6854LC optical specification 80 8 optical specification 8.1 lens characteristics note: the module ir filter cut-off wavelength is 650 nm. table 64. lens design characteristics for first source lens supplier parameter value 4-element plastic lens - f/number 2.8 effective focal length 3.26mm (prima ry wavelength 587.56 nm used) horizontal fov 57.8 closest focusing distance <300 mm with daf distortion tv: -0.3 (typ)% absolute: <|1.0%| across whole field (by design) relative illumination (lens only) 46% at 1.0 field. maximum illumination decrease over 10% of image height. (lens only) 12% spectral weighting: wavlength (nm) weight 656.28 151 587.56 318 546.07 312 486.13 157 435.84 49 404.66 13 lateral chromatic aberration from blue ( =435nm) to red ( =656nm) < |1.8 um| coating reflectance - all surfaces are coated. at least 50% of all surfaces must fulfil this specification. < 400nm 400 - 670nm >670nm no limitation 1.0% absolute, 0.35% avg straight line with a slope of < 3% / 100nm maximum chief ray angle 28.2
optical specification VX6854LC 80/114 docid027110 rev 2 8.2 text, 1d and 2d code reading the VX6854LC camera module features a supermacro mode dedicated to business card and text reading as well as barcode and 2d qr code reading using a monochrome image. figure 29. examples of barcode and qr code note: the above performances were achieved on VX6854LC in supermacro mode through st?s image processing pipe and with standard mobile phone application qr decoder software. refer to the ?edof application note? for recommendations on host processing pipe tuning for qr/barcode reading. table 65: qr code (2d) re solution reading capability performances working distances (cm) qr code 0.339 mm 25-28cm qr code 0.4 mm 20-30cm qr code 0.5 mm 15-30cm qr code 0.6 mm 15-30cm qr code 0.7 mm 15-30cm qr code barcode
docid027110 rev 2 81/114 VX6854LC application 102 9 application 9.1 schematic figure 30. mobile camera application 1. ccp 100r termination may be internal to sublvds receiver (for example, stv0986). 2. no external supply decoupling capac itors are required as the necessary components are integrated into the module. VX6854LC 1.8v extclk data+ clk- gnd scl sda 1.8v external clock power down signal 100r 100r 4.7k xshutdown data- clk+ sublvds data sublvds clock cci control lines vdig vcap 2.8v vana vcap
application VX6854LC 82/114 docid027110 rev 2 9.2 personality file the personality file as specified in smia 1.0 part 3.1:software and application specification is detailed below: smia_personality_file_id : 2.9 date : 2010-oct-15 manufacturer_id : 1 model_id : 854 revision_number : silicon cut2.1 setting : register_override matrix optimisation 7aug2009 (d65) matrix_element_redinred = 1.934 matrix_element_grninred = -0.586 matrix_element_bluinred = -0.348 matrix_element_redingrn = -0.401 matrix_element_grningrn = 1.582 matrix_element_bluingrn = -0.181 matrix_element_redinblu = -0.052 matrix_element_grninblu = -0.635 matrix_element_bluinblu = 1.687 0x1122 = 0x0002 // max_vt_sys_clk_div 0x111c = 0x44480000 // max_pll_op_freq = 800mhz 0x1500 = 0x0400 // fifo_capability = 1023 pixels setting : register_reprogram_once // require to load the following files: // VX6854LC_cut2_patch06.txt - fixes the gph, dark cal and hfpn bugs. also sets the analog msrs. 0x0b06 = 0x00 // single_defect_correct = disable -> this enables the ringcorrect 0x0b07 = 0x80 // single_defect_correct_weight = auto 0x0b08 = 0x01 // couplet_correct = enable 0x0b09 = 0x4f // couplet_correct_weight 0x0b83 = 0x00 // edof sharpness 0x0b84 = 0x20 // edof denoising 0x0b85 = 0x20 // edof noise vs. details 0x0b88 = 0x8000 // edof_focus_distance = automatic from preview 0x317e = 0x11 // iq av_r2_shift 0x317f = 0x09 // iq av_slant_shift //additional settings if binning disabled n/a //additional settings for binning 2x2 0x0383 = 0x03 // x-odd inc
docid027110 rev 2 83/114 VX6854LC application 102 0x0387 = 0x03 // y-odd inc 0x0900 = 0x01 // enable binning mode 0x0901 = 0x22 // binning type 0x0902 = 0x04 // binning weighting 0x1716 = 0x0197// fine_integration_time_min_bin 0x1718 = 0x080f// fine_integration_time_max_margin_bin // // set ext clk freq (default =6mhz) 0x0136 0xxxxx // note this should be set before loading the patch setting : register_reprogram_every // the white balance gains must be written to the sensor every time the white balance gains change. //end
edof control VX6854LC 84/114 docid027110 rev 2 10 edof control the VX6854LC module uses a fixed focused lens with optical aberrations that the edof reconstruction engine is designed to recover the resolution and increase the depth of field in the range of 20 cm to infinity. the focus is tuned for far distances > 2 m but for closer distances where a standard fixed focus camera would show a blur image, the edof correction is capable of signif icantly recovering the resolution. figure 31. what is sharp? facts about optics ? the depth of focus narrows with reduction in object distance or with aperture increase. ? if the lens is focussed at the hyper-focal distance, the sharpness will be the same from hyperfocal/2 to infinity. ? the depth of field is defined by the range of scene distances that appears acceptably sharp in the image. ? the size of a pixel (1.75 um) can be defined as a blurred spot. a blurred spot smaller than 1.75 um is registered as sharp. above that value the spot will look blurred (refer to circle of confusion graph).
docid027110 rev 2 85/114 VX6854LC edof control 102 considering the above points, edof aims to make the blur spot invariant (or change its reference) over a range of objects distances, thus defeating the obvious geometric optical effects to enhance the depth of field. the plot below shows the edof main principle: figure 32. edof main principle 10.1 edof capabilities the edof reconstruction engine is applied to the image after defect correction. it has denoising, sharpening, deconvolution algorith ms among others that allow recovering the resolution. it is advised that the end user does not use the edof ip as a sharpness block. edof has a depth of field recovery role. oversharpening the image using edof before the host image processing might alter the final image quality. the edof reconstruction engine can improve the depth of field for a colored image in the range of 30 cm to infinity and for a monochrome image below 30 cm. the edof block works with ranges of distances in four modes for which the correction applied will be different: ? super macro mode: < 30 cm ? macro mode: 30 to 49 cm ? portrait: 50 to 119 cm ? landscape: 120 cm to infinity the distance estimation analyzes gradients and relative sharpness among channels. it first returns a measure of the sharpest chann el in the image giving a macro ?vote? when the sharpest channel is the blue one, portrait when it?s the green and landscape when it?s the red.
edof control VX6854LC 86/114 docid027110 rev 2 the relative sharpness among channel varies with the object distance but also in the field of the image (field curvature), so the votes are then weighted by calibration data in order to obtain the most appropriate mode or distance at the output. note: the aim of the distance estimation is not to obtain a precise distance but to select the best parameterization for the correction to be applied in capture, therefore the returned distance or specified distances range is indicative only. like an auto-focus module: ? the algorithm has failure cases, but the corr ection is constrained in order to always have acceptable image quality even if not optimal. ? for a single image several modes are often possible and giving same level of image quality. ? for overlap distances (between macro and po rtrait modes, or between portrait and landscape modes), two of the channels may have the same level of sharpness, so any of the two corresponding distances could be returned, depending on scene content and field curvature of the module. ? for scenes with objects at different distan ces, any of the three distances could be returned depending on content of the scene, field curvature of the module and spatial weights used for estimation (edof_estimation_control). supermacro mode is used for bar code and business card reading. supermacro mode uses a monochrome image. below 30 cm distance, the mtf is lost and there is too little green and red pixel information to build a colorized image. however, the blue pixel has enough mtf to reconstruct a monochrome image. 10.2 control interface the modules have a 100 khz/400 khz i 2 c compatible 2-wire contro l interface. it uses the smia 16-bit index, 8-bit data message format. the cci interfaces allows the programming of the edof control registers.
docid027110 rev 2 87/114 VX6854LC edof control 102 10.3 edof control registe rs [0x0b80 to 0x0b8a] table 66 lists the different registers that the end user can configure to tune the edof block. 10.3.1 edof_mode (0xb80) the edof block can be disabled or enabled. the in terest of disabling this block would be to save some power consumption. when enabling edof, two modes are available: ? estimation mode this mode is dedicated to image preview (v iewfinder) only. edof correction is not being applied but statistics are gathered for distance estimation. estimation mode can be full resolution or subsampled or binned image up to a maximum of x4 in both directions. if too much subsampling is perf ormed the image out of the sensor becomes sharp and focus distance estimation is not possible. ? application mode this is used for capture (or snapshot). the edof distance calculated during estimation is applied to the image. the application mode can only be enabled after the estimation mode has been selected, othe rwise the edof correction will not be applied. edof cannot be applied to subsampled or binned images as it is not necessary to correct images when they are subsampled as the im age blur introduced by the lens does not table 66. edof registers [0x0b80 to 0x0b8a] index byte register name data type default type comment 0x0b80 edof_mode 8ui 00 rw edof control 0 - edof disabled (power saving) 1 - edof application (capture) 2 - edof estimation (preview) 0x0b82 edof_est_focus_dista nce 8ui 32 ro the estimated focus point (cm) 0x0b83 edof_sharpness 8ui 00 rw edof sharpness control 0 - 127: manual mode 0x0b84 edof_denoising 8ui 00 rw edof denoising control 0 - 127: manual mode 0x0b85 edof_module_specific 8ui 00 rw edof noise vs. details control 0 - 127: manual mode 0x0b88 hi edof_focus_distance 16ui 00.32 rw value supplied by the host which is used by module for focus distance (in cm). 0x0000 to 0x7fff - manual mode 0x8000 to 0xffff - auto mode 0x0b89 lo 0x0b8a edof_estimation_cont rol 8ui 00 rw edof estimator control 0/1 - uniform 2 - centre weight 4 - large spot 8 - narrow spot
edof control VX6854LC 88/114 docid027110 rev 2 need to be corrected when images are downscaled. no focus distance estimates are performed in application mode, even in multi-shot mode. for preview mode, set the 0x0b80 register in estimation mode 0x0b80 = 0x02; // edof enabled for estimation mode for capture mode, set the 0x0b80 register in application mode 0x0b80 = 0x01; // edof enabled for application mode note: before enabling application mode, estimation mo de has to be applied for a minimum of one frame so as to estimate the edof focus distance. this information is used in application mode when the image data is corrected. if estimation mode is not enabled prior to application mode, no correction will be applied to th e snapshot image. 10.3.2 edof_est_focus_distance (0x0b82) the edof_est_focus_distance register ( 0x0b82) is read only. this register tells the user the estimated focus point (cm) that the edof function has calculated. 10.3.3 edof tuning sliders (0xb83 to 0x0b85) the three key registers for the end user tuning are the sharpness, denoising and noise versus detail registers. ? edof_sharpness (0x0b83) value ranges from 0 to 127. the higher the value the more sharpening is applied. higher values result in high contrasted edges being more sharpened but the noise level in uniform areas will not suffer. figure 33. example images with different settings for sharpness slider sharpness=0x00 sharpness=0x60 sharpness=0x40
docid027110 rev 2 89/114 VX6854LC edof control 102 ? edof_denoising (0x0b84) value ranges from 0 to 127. the higher the value the stronger the denoising to be applied. higher values results in reduced noise in uniform areas. figure 34. example images with different settings for denoising slider ? edof_module_specific (noise vs. details) (0x0b85) value ranges from 0 to 127. defines the weig ht of the sharpening versus the denoising weight. the higher the value the more weight is given to sharpness (that is, lower denoising weight). the lower the value, the more denoising weight is being applied. if sharpness (0x0b83) and denoising (0x0b84) re gisters are set to 0, then whatever this register value is, it will make no difference. figure 35. example images with differen t settings for noise vs. details slider note: 1 even with the above three registers values set to 0, a correction is being applied and will show a significant improvement versus no correction at all. 2 the tuning sliders do not operate in supermacro mode. recommended settings for recommended settings for the edof sliders (0x0b83 to 0x0b85) refer to the relevant personality file. denoising=0x00 denoising=0x60 denoising=0x40 noisevsdetails=0x00 noisevsdetails=0x60 noisevsdetails=0x40
edof control VX6854LC 90/114 docid027110 rev 2 10.3.4 edof focus distance (0x0b88) for automatic mode, the value range is 0x8000 to 0xffff. whatever value is selected within this range, automa tic distance estimation will be en abled. st recommend setting the edof estimation mode to automatic mode. in this mode, when the user selects application mode, the edof processi ng will automatically use the last estimate of the focus distance obtained in estimation mode. for manual mode, the value to be set in the register is the value of the distance in cm. the range is 0x0000 to 0x7fff. if you want to use one of the following modes, apply the following values: ? super macro mode: 0 to 29 cm ? macro mode: 30 to 49 cm ? portrait: 50 to 119 cm ? landscape: 120 to 32767 cm whatever value is selected within a partic ular range will produce the same result. for example, applying any value between 0 and 29 selects super macro mode and produces the same result in the final image. super macro mode only works in manual mode. refer to section 10.4: super macro mode for more detailed information. procedure to test distance estimation reference test scene: black and white chart (for example sfr chart or iso12233), under d65 illuminant, minimal analog gain. ensure that the streaming frames are correctly exposed and that the white balance gains are written to the sensor. place the sensor at the minimum distance (that is, lower macro range distance) and then move the module gradually away from the scene the estimated distance should change according to the distances quoted below: ? macro mode: 30 cm ? portrait: 50 cm ? landscape: 120 cm note: 1 there is always an overlap between two co nsecutive modes, it might therefore be possible that the mode switch may not be exactly done at the given boundary. 2 the distances quoted above are given for d65, results may vary slightly for other illuminants. for instance, if the s witch is 50 cm in daylight, it is closer to 40 cm for tungsten illuminants. 3 it?s not always possible to shoot charts at land scape distances. in this particular case, shoot an outdoor image with objects at infinity: the estimated distance should be landscape.
docid027110 rev 2 91/114 VX6854LC edof control 102 10.3.5 edof estimati on control (0x0b8a) this register selects the region of interest (r oi) on which to apply the distance estimation processing. four different rois are available: 0 or 1: uniform 2: center-weighted 4: spot- large 8: spot narrow considering the above order, with increasing values, the esti mation will increasingly focus on objects in the centre of the image. the processing time is identical for all cases. figure 36. focus strategy weightings 10.4 super macro mode unlike the other modes (macro, portrait and landscape), super macro mode cannot be managed by the automated distance range estimato r. the reason is that at distances below 30 cm, there is very little information in green and red channels though there is a significant energy in the blue channel. the distance esti mator needs the four color channel information to estimate the distance. be low 30 cm, unless the distance is manually programmed using register 0x0b88, the edof co rrection will not be accurate. for text or bar code reading, a monochromatic image can be used. edof super macro mode can be used for that purpose as the ed of reconstruction engine would use the blue channel information to calculate the suitable sharpness and denoising. to enable super macro mode, the user has to program manually the register 0x0b88 to set a value for distances below 30 cm. the register value being the value of the distance in cm. it is important to note that as the super macr o mode uses one color channel, the host has to consider using only the blue channel info rmation to build a monochromatic image and the following features need to be disabled or restricted: ? lens shading correction: only apply blue channel correction ? disable white balance correc tion in the host: the white balance gains must still be calculated and written to the sensor ? no demosaicing ? disable any 4 channel gain dependant block in the host ? apply black and white matrix, rather than color matrix. (0 1 0, 0 1 0, 0 1 0) narrow spot large spot center 32 2 2 2 2 2 22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 0 1 0 0 00 0 0 0 0 0 0 0 00 00 0 1 1 1 1 1 1 1 1 uniform 1 1 1 1 1 11 11 1 11 1 11 11 1 1 1 11 1 11 the image is arranged as 5x5 regions for the weightings.
edof control VX6854LC 92/114 docid027110 rev 2 10.5 edof and white balance the edof reconstruction engine requires the white balance gains to be programmed by the host (by i 2 c writes) to the color feedback register (0x0b8e to 0x0b95) of the sensor. these gains are also used for the sensor adap tive lens shading correction if enabled. the gains must be written to the sensor every time that the white balance gains change. the white balance gains are required in both estimation and application modes. the four host white balance gains to be programmed are listed in table 67 . table 67. color feedback registers [0x0b8c - 0x0b95] index byte register name data type default type comment 0x0b8e hi host_wb_stats_green_red 16ur 01.00 rw white balance gains to be applied by the host. these are used by the edof and the adaptive av to estimate the color temperature of the scene. 0x0b8f lo 0x0b90 hi host_wb_stats_red 16ur 01.00 rw 0x0b91 lo 0x0b92 hi host_wb_stats_blue 16ur 01.00 rw 0x0b93 lo 0x0b94 hi host_wb_stats_green_blue 16ur 01.00 rw 0x0b95 lo
docid027110 rev 2 93/114 VX6854LC image optimization 102 11 image optimization the sensor has the following image optimizations on the sensor: ? mapped couplet correction ? dynamic couplet and singlet correction ? lens shadin g correction figure 37 shows the processing pipe. note that defect correction must be enabled as it occurs before the edof processing. figure 37. processing pipe lens shading correction defect correction edof imaging array
image optimization VX6854LC 94/114 docid027110 rev 2 11.1 defect correction the defect correction algorithm dynamically detects and corrects single and couplet defective pixels in the imaging array. the weight of both correction filters can be adjusted. for recommended settings refer to the personality file. an image showing an example of defective pixels is shown in figure 38 . figure 38. image showing defective pixels a simplified block diagram of the defective correction block is shown in figure 39 . figure 39. block diagram of dy namic defect correction block
docid027110 rev 2 95/114 VX6854LC image optimization 102 an example of an image before and after correction is shown in figure 40 . figure 40. dynamic defect correction output example an example of a corrected bayer pattern is shown in figure 41 . figure 41. corrected bayer pattern original image corrected image colorized original bayer colorized corrected bayer
image optimization VX6854LC 96/114 docid027110 rev 2 11.2 mapped couplet correction (bruce) the mapped couplet de fect correction filter is designed to intelligently correct the first defect in a couplet thereby changing a couplet into a single pixel defect. single pixel defects can then be corrected using the dynamic defect correction filter. the mapped couplet correction filter requires exact coordinate information for each of the couplets to be repaired. the couplet coordinat es are stored in non-volatile-memory (nvm) during production test. the mapped couplet corr ection filter does not operate in binning mode or in sub sample mode and is automatically disabled. the mapped couplet correction is controlled by register 0x0b05: 0 - disable 1 - enable 11.3 lens shading correction the sensor has an adaptive (four color temperat ure) lens shading correction function which can be used to reduce the effect of roll off in the optical system. correction is carried out individually for all four color planes, each gain is calculated based on the distance from the image centre to the pixel in question using a two factor polynomial (r2 and r4). in order to optimize the adaptive lens shading algorithm, the coefficients for each device are calculated under d65 lighting conditions and programmed in the nvm memory at production test. settings for three other color temperatures (c ool white, u30, and horizon) are calculated from characterization data and these are stored in the nvm memory. the calculation of the color temperature is performed by the sensor using the color feedback registers. therefore it is necessary for the host to supply the sensor with the white balance gains. the lens shading function can be used with the profile1 and profile 2 scaler and with crop and sub-sampling. the lens shading correction is controlled by register 0x0b00: 0 - disable 1 - enable the correction applied is 75%. figure 42. lens shading images original image corrected image
docid027110 rev 2 97/114 VX6854LC nvm contents 102 12 nvm contents the sensor has the following contents in the nvm: ? revision and traceability data ? defect data (used on-chip, described in section 11.2 ) ? lens shading 4 channel radial corrector data (used on-chip, described in section 11.3 ) ? sensitivity data (to be used by the host) 12.1 sensitivity data this data is not used by the sensor but ca n be used by the host to calibrate the awb system. the sensitivity data is measured at fmt for each device for one color temperature d65 (fluorescent phillips graphica pr o 965). each of the four colo r channel values are recorded. the 10-bit average of the central 10% of th e image (10% of image width, 10% of image height) is recorded, the pedestal is included in the value. the on board lens shading correction is disabled. the analog gain is set to x1. 12.2 nvm map the sensor must be in software standby to read the nvm. in order to read the nvm the following registers must be programmed. 0x3e04 = 1 - power-up the nvm 0x3640 = 0 - access nvm register space the registers should be reset after reading the nvm to the following: 0x3e04 = 0 - power-down the nvm 0x3640 = 1 - disable access to nvm register space table 68. nvm map index data transfer page & page value segment bit number comments 76543210 0xfc00 0,0 0x00 not used 0xfc01 0,1 0x00 0xfc02 0,2 0x00 0xfc03 0,3 0x00
nvm contents VX6854LC 98/114 docid027110 rev 2 0xfc04 0,4 st payload - module data 0x03 module model id: 0x0356 (854d) 0xfc05 0,5 0x56 0xfc06 0,6 modulerevmajor[7:0] 00: unprogrammed 01: es1.0 02: es2.0 0xfc07 0,7 00 modulerevminor 0xfc08 0,8 01 modulemanufid (st) 0xfc09 0,9 year month 0xfc0a 0,10 day moduledatephase moduledatephase[2: 0] 00: ts 01: es 02: cs 03: mp 0xfc0b 0,11 serialnumber[31:24] serial numbering, [31:24]: tester code [23:0]: seconds since midnight 0xfc0c 0,12 serialnumber[23:16] 0xfc0d 0,13 serialnumber[15:8] 0xfc0e 0,14 serialnumber[7:0] 0xfc0f 0,15 0 0 0 0 00 sensorrevno[3:0] 0xfc10 0,16 st payload - defect correction defectcount[15:8] number of defects 0xfc11 0,17 defectcount[7:0] 0xfc12 0,18 coupletxcoord[11:4] coordinates of first defect 0xfc13 0,19 coupletxcoord[3:0] 0 coupletycoord[10:8] 0xfc14 0,20 coupletycoord[7:0] variable amount of bytes depending on the number of defects programmed. gap gap so that av data starts on a word boundary. this is programmable depending on the number of couplets stored. table 68. nvm map (continued) index data transfer page & page value segment bit number comments 76543210
docid027110 rev 2 99/114 VX6854LC nvm contents 102 av_start_ addr st payload - adaptive av coefficients for cast3 (d65) av_r 2 _red_cast3[7:0] av_start_ addr+1 av_r 2 _greenred_cast3[7:0] av_start_ addr+2 av_r 2 _greenblue_cast3[7:0] av_start_ addr+3 av_r 2 _blue_cast3[7:0] av_start_ addr+4 av_r 4 _red_cast3[7:0] av_start_ addr+5 av_r 4 _greenred_cast3[7:0] av_start_ addr+6 av_r 4 _greenblue_cast3[7:0] av_start_ addr+7 av_r 4 _blue_cast3[7:0] av_start_ addr+8 av_horiz_slant_coeff_red_cast3[7:0] av_start_ addr+9 av_horiz_slant_coeff_greenred_cast3[7:0] av_start_ addr+10 av_horiz_slant_coeff_greenblue_cast3[7:0] av_start_ addr+11 av_horiz_slant_coeff_blue_cast3[7:0] av_start_ addr+12 av_ver_slant_coeff_red_cast3[7:0] av_start_ addr+13 av_ver_slant_coeff_g reenred_cast3[7:0] av_start_ addr+14 av_ver_slant_coeff_greenblue_cast3[7:0] av_start_ addr+15 av_ver_slant_coeff_blue_cast3[7:0] av_start_ addr+16 av_dc_coeff_red_cast3[7:0] av_start_ addr+17 av_dc_coeff_greenred_cast3[7:0] av_start_ addr+18 av_dc_coeff_greenblue_cast3[7:0] av_start_ addr+19 av_dc_coeff_blue_cast3[7:0] table 68. nvm map (continued) index data transfer page & page value segment bit number comments 76543210
nvm contents VX6854LC 100/114 docid027110 rev 2 av_start_ addr+20 st payload - adaptive av coefficients for cast2 av_r 2 _red_cast2[7:0] av_start_ addr+21 av_r 2 _greenred_cast2[7:0] av_start_ addr+22 av_r 2 _greenblue_cast2[7:0] av_start_ addr+23 av_r 2 _blue_cast2[7:0] av_start_ addr+24 av_r 4 _red_cast2[7:0] av_start_ addr+25 av_r 4 _greenred_cast2[7:0] av_start_ addr+26 av_r 4 _greenblue_cast2[7:0] av_start_ addr+27 av_r 4 _blue_cast2[7:0] av_start_ addr+28 st payload - adaptive av coefficients for cast1 av_r 2 _red_cast1[7:0] av_start_ addr+29 av_r 2 _greenred_cast1[7:0] av_start_ addr+30 av_r 2 _greenblue_cast1[7:0] av_start_ addr+31 av_r 2 _blue_cast1[7:0] av_start_ addr+32 av_r 4 _red_cast1[7:0] av_start_ addr+33 av_r 4 _greenred_cast1[7:0] av_start_ addr+34 av_r 4 _greenblue_cast1[7:0] av_start_ addr+35 av_r 4 _blue_cast1[7:0] table 68. nvm map (continued) index data transfer page & page value segment bit number comments 76543210
docid027110 rev 2 101/114 VX6854LC nvm contents 102 av_start_ addr+36 st payload - adaptive av coefficients for cast0 av_r 2 _red_cast0[7:0] av_start_ addr+37 av_r 2 _greenred_cast0[7:0] av_start_ addr+38 av_r 2 _greenblue_cast0[7:0] av_start_ addr+39 av_r 2 _blue_cast0[7:0] av_start_ addr+40 av_r 4 _red_cast0[7:0] av_start_ addr+41 av_r 4 _greenred_cast0[7:0] av_start_ addr+42 av_r 4 _greenblue_cast0[7:0] av_start_ addr+43 av_r 4 _blue_cast0[7:0] av_start_ addr+44 st payload - adaptive av nred gain casts normalised_red_gain_cast3[15:8] av_start_ addr+45 normalised_red_gain_cast3[7:0] av_start_ addr+46 normalised_red_gain_cast2[15:8] av_start_ addr+47 normalised_red_gain_cast2[7:0] av_start_ addr+48 normalised_red_gain_cast1[15:8] av_start_ addr+49 normalised_red_gain_cast1[7:0] av_start_ addr+50 normalised_red_gain_cast0[15:8] av_start_ addr+51 normalised_red_gain_cast0[7:0] table 68. nvm map (continued) index data transfer page & page value segment bit number comments 76543210
nvm contents VX6854LC 102/114 docid027110 rev 2 0xfdf4 7,52 sensitivity_re d[9:8] the measured light level is recorded per bayer color channel for diffuse d65 illumination, av off, roi = central 10% of image height and width, including pedestal. these values can be used as input into the isp awb algorithm to normalise the sensor response to match that of the ?golden? sensor used to set-up the awb tilts. not used by VX6854LC 0xfdf5 7,53 sensitivity_red[7:0] 0xfdf6 7,54 sensitivity_gr eenred[9:8] 0xfdf7 7,55 sensitivity_greenred[7:0] 0xfdf8 7,56 sensitivity_gr eenblue[9:8] 0xfdf9 7,57 sensitivity_ greenblue[7:0] 0xfdfa 7,58 sensitivity_bl ue[9:8] 0xfdfb 7,59 sensitivity_blue[7:0] 0xfdfc 7,60 mapversion[7:0] 0xfdfd 7,61 testprogramrevmaj[7:0] 0xfdfe 7,62 testprogramrevmin[7:0] 0xfdff 7,63 table 68. nvm map (continued) index data transfer page & page value segment bit number comments 76543210
docid027110 rev 2 103/114 VX6854LC defect categorization 110 13 defect categorization 13.1 pixel defects illuminated defects are tested wit h a flat field illumination and a pass-fail criteria that is a percentage deviation from a local mean. in order that the sensor can be effectively tested in a reasonable test time, it is necessary to put the limits of gain error above the normal noise distribution of photon shot no ise and sensor noise otherwis e false single pixel fails will be detected. a typical defect criteria for single-pixel gain errors is 9%. in fact, any element in the array outside 9% is a ?minor? fail, and outside of 25% is a ?major? fail. note that the defect detection method is applied to raw bayer images. 13.2 sensor array area definition for specific aspects of pixel defect testing th e image sensor array is subdivided into two regions as illustrated in figure 43 . figure 43. VX6854LC pixel defect test area the inner array in figure 43 is centre justified, in the x an d y axis, with respect to the outer array. the inner array is 50% of the full width and 50% of the full height of the larger outer array, therefore the inner array is one quarter of the area of the outer array. outer array inner array 1032 pixels 2064 pixels 1552 pixels 776 pixels
defect categorization VX6854LC 104/114 docid027110 rev 2 13.3 pixel fault numbering convention the pixel notation is described in figure 44 . for the purposes of the test the 3x3 array describes nine bayer pixels of a common color, that is, all the pixels will either be red, green (the green pixels are split over 2 common channels, green1 and green2) or blue. the pixel under test is x . if a pixel under test is on the edge, the array is reduce to its existing neighbor pixels (that is, th e first pixel uses only a 2x2 array). figure 44. pixel numbering notation 13.4 single pixel faults stmicroelectronics defines a si ngle pixel fail as a failing pixe l with no adjacent failing same color neighbours. a single pixel fail can be a stuc k at white where the output of the pixel is permanently saturated regardless of the level of incident light and exposure level, a stuck at black where the pixel output is zero regardless of the level of incident light and exposure level (major fail) or simply a pixel that differs from it?s immediate neighbours by more than the test threshol d (minor fail). the example in figure 45 assumes that pixel x is a fail. for this pixel to be a single pixel fail the pixels at positions [0],[1],[2 ],[3],[4],[5],[6] and [7] must be ?good? pixels that pass final test. the implemented te st program will pass a sensor with up to the defined limit of single pixel faults per color channel. defect correction algorithms will correct the pixel faults in the final image. figure 45. single pixel fault [0] [1] [2] [7] x [3] [6] [5] [4] [0] [1] [2] [7] x [3] [6] [5] [4]
docid027110 rev 2 105/114 VX6854LC defect categorization 110 13.5 couplet definition a failing pixel at x with a failing pixel at position [0], [1], [2], [3], [4], [5], [6 ] or [7] such that there is a maximum of two fa iling pixels from the group of nine pixels illustrated in figure 46 . the example shown in figure 46 has the centre pixel and the pi xel at position [7] failing the test criteria. figure 46. general couplet example the basic couplet definition is further subd ivided into minor and major couplets. with respect to the example in figure 46 , a minor couplet is defined as a defect pixel pair where one pixel can be an extreme fail, that is a stuc k at black or stuck at white, but the second pixel in the pair must differ from the local pixel average by less than 25% of that average value. if the second pixel in the couplet differs by more than 25% of the local pixel average value then this would be defined as a major couplet. in addition, couplets will be classified as being in the inner or outer area. 13.6 physical aberrations a specific test algorithm is also applied in pr oduction to identify an d reject samples that display defocused artefacts often referred to as blemishes or shapes. these artefacts are caused by scratches or contamination in the optical path away from the focal plane for example, on the ir glass or lens. the test requires two regions to be defined: ? a small area: 9 by 9 pixels with the pixel under test at the centre of this area (shaded blue in figure 47 ) ? a large region, 31 by 31 pixels (shaded red in figure 47 ) figure 47. test region definition [0] [1] [2] [ x ]x [3] [6] [5] [4] 9 pixels 9 pixels 31 pixels 31 pixels small area large area
defect categorization VX6854LC 106/114 docid027110 rev 2 an average value is calculated for both the ?small? and ?large? areas. the areas are then scanned across each colo r channel separately. figure 48. scan array for blemish the next stage of the test is the creation of a pixel map for each color channel with the coordinates of the failing pixels. see figure 49 . figure 49. fail map a pixel location is identified as a fail in t he map if it satisfies the following criteria: small_average < large_average - (1.2% of large_average) or small_average > large_average + (1.2% of large_average) blemish
docid027110 rev 2 107/114 VX6854LC defect categorization 110 the contents of the fail map det ermine whether the sensor fails the physical aberration test. the module fail criteria is: pass if: <= 82 contiguous pi xel entries in the failure map for each color channel. an example of contiguous pixels entries is given in figure 50 . figure 50. contiguous pixel example the group of pixels enclosed in the circle are contiguous, that is ever y pixel in the group is attached to at least one neighbouring pixel. the other pixel entries shown in the figure are non contiguous as they have no touching neighbours.
mechanical VX6854LC 108/114 docid027110 rev 2 14 mechanical figure 51. VX6854LC outline drawing - sheet 1 of 3
docid027110 rev 2 109/114 VX6854LC mechanical 110 figure 52. VX6854LC outline drawing - sheet 2 of 3
mechanical VX6854LC 110/114 docid027110 rev 2 figure 53. VX6854LC outline drawing - sheet 3 of 3
docid027110 rev 2 111/114 VX6854LC user precaution 111 15 user precaution as is common with many cmos imagers the camera should not be pointed at bright static objects for long periods of time as permanent damage to the sensor may occur. 16 acronyms and abbreviations table 69. acronyms and abbreviations acronym/ abbreviation definition ccp compact camera port cci camera control interface csi camera serial interface edof extended depth of field emi electro magnetic interference eof end of frame fe frame end fps frames per second fs frame start hwa hardware accelerator i2c inter icbus lsb least significant byte lvds low voltage differential signaling mbps megabits per second msb most significant byte msp manufacturer specific pixels pck pixel clock pcm pulse code modulation pll phase locked loop ro read only rw read/write smia standard mobile imaging architecture sof start of frame sublvds sub-low voltage differential signaling
ecopack ? VX6854LC 112/114 docid027110 rev 2 17 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark.
docid027110 rev 2 113/114 VX6854LC revision history 113 18 revision history table 70. document revision history date revision changes 27-oct-2014 1 initial release. 09-sep-2015 2 updated disclaimer
VX6854LC 114/114 docid027110 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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